Methods and structures for forming microstrip transmission lines on thin silicon carbide on insulator (SICOI) wafers

Patent metadata

Field	Value
Publication number	US-9761445-B2
Application number	US-201615082500-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Dec 13, 2013
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

First claim

What is claimed is:

1. A method, comprising:
(A) providing a structure having: a layer comprising silicon; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon;
(B) forming a Group III-V device in the III-V layer and a strip conductor connected to the Group III-V device;
(C) removing a silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and
(D) forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

2. The method recited in claim 1 wherein the layer comprising silicon is <111> silicon.

3. The method recited in claim 1 wherein the layer comprising silicon is silicon carbide.

4. A method, comprising:
providing a structure having: (A) a layer comprising silicon and a first silicon dioxide layer over a silicon carbide layer; and (B) a silicon layer and a second silicon dioxide layer over the silicon layer; the first silicon dioxide layer being bonded to the second silicon dioxide layer; wherein the first silicon dioxide layer and the second silicon dioxide layer provide a bonding structure;
bonding the first silicon dioxide layer to the second silicon dioxide layer;
growing a Group III-V layer on an upper surface of the layer comprising silicon;
forming an active device in the Group III-V layer together with a strip conductor connected to the formed device;
successively removing the silicon layer and the second silicon dioxide layer to expose a bottom surface of the layer comprising silicon; and
forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon, the strip conductor, the ground plane conductor and a portion of the silicon layer comprising silicon providing a portion of a microstrip transmission line.

5. The method recited in claim 4 wherein the upper surface of the layer comprising silicon of the first structure is polished to reduce the thickness of the layer comprising silicon prior to forming the Group III-V layer.

6. The method recited in claim 4 wherein the layer comprising silicon is <111> silicon.

7. The method recited in claim 4 wherein the layer comprising silicon is silicon carbide.

8. The method recited in claim 5 wherein the layer comprising silicon is silicon.

9. The method recited in claim 5 wherein the layer comprising silicon is silicon carbide.

10. The method recited in claim 4 wherein Group III-V layer is formed on the upper surface of the layer comprising silicon before the bottom surface of the layer comprising silicon is polished to reduce its thickness.

11. The method recited in claim 10 wherein the layer comprising silicon is silicon.

12. The method recited in claim 10 wherein the layer comprising silicon is silicon carbide.

Assignees

• Raytheon Co

Inventors

• Laroche Jeffrey R
• Ip Kelly P
• Kazior Thomas E

Classifications

• H01P11/003

  Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines · CPC title

• H10P90/1904

  Preparing vertically inhomogeneous wafers · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1922

  using silicon etch back techniques, e.g. BESOI or ELTRAN · CPC title