Methods and systems for address mapping between host and expansion devices within system-in-package (SiP) solutions

Patent metadata

Field	Value
Publication number	US-9176916-B2
Application number	US-201313775313-A
Country	US
Kind code	B2
Filing date	Feb 25, 2013
Priority date	Feb 25, 2013
Publication date	Nov 3, 2015
Grant date	Nov 3, 2015

Abstract

Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.

First claim

What is claimed is:

1. A die-to-die port (DTDP) system having plug-and-play connectivity, comprising:
a DTDP host device within a first integrated circuit; and
a DTDP expansion device within a second integrated circuit;
the DTDP host device within the first integrated circuit, comprising:
port interconnect circuitry having a plurality of ports and decode circuitry, the decode circuitry being configured to direct communications between the plurality of ports based upon a host…

Assignees

• Miller Gary L
• Freescale Semiconductor Inc

Inventors

• Miller Gary L

Classifications

• H10W10/181

  Electricity · mapped topic

• H10P90/1914

  Electricity · mapped topic

• H10W95/00

  Electricity · mapped topic

• G06F13/409 Primary

  Physics · mapped topic

• H01L21/50

  Electricity · mapped topic