Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
Process for fabricating a semiconductor-on-insulator substrate
US2015311110A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015311110-A1 |
| Application number | US-201314441473-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 25, 2013 |
| Priority date | Nov 20, 2012 |
| Publication date | Oct 29, 2015 |
| Grant date | — |
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- Title
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Abstract
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The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment step is designed to partially dissolve the silicon dioxide layer, the heat treatment step being carried out in a non-oxidizing atmosphere and the pressure of the non-oxidizing atmosphere being lower than 0.1 bar.
First claim
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1 . A fabrication process for fabricating a plurality of semiconductor-on-insulator structures, comprising: providing a plurality of semiconductor-on-insulator structures each including a carrier substrate, a semiconductor layer, and an insulator layer between the carrier substrate and the semiconductor layer, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm; and after providing the plurality of semiconductor-on-insulator structures; heat treating the plura…
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Classifications
Electricity · mapped topic
- H10P90/1914Primary
Electricity · mapped topic
Electricity · mapped topic
- H10P90/1906Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2015311110A1 cover?
- The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment ste…
- Who is the assignee on this patent?
- Soitec Silicon On Insulator
- What technology area does this patent fall under?
- Primary CPC classification H10P90/1914. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Oct 29 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).