Substrate correction device, substrate lamination device, substrate processing system, substrate correction method, substrate processing method, and semiconductor device manufacturing method
US-2024404859-A1 · Dec 5, 2024 · US
Handle Substrate and Composite Wafer for Semiconductor Device
US2015357221A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2015357221-A1 |
| Application number | US-201514829808-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 19, 2015 |
| Priority date | Jan 6, 2014 |
| Publication date | Dec 10, 2015 |
| Grant date | — |
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Abstract
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In a handle substrate for a composite wafer for a semiconductor, particles from the wafer with a notch formed therein are reduced. The handle substrate 1 A or 1 B for the composite wafer for the semiconductor is formed of a polycrystalline ceramic sintered body, and includes a notch 2 A or 2 B in its outer peripheral portion. The notch is formed with an as-sintered surface.
First claim
Opening claim text (preview).
1 . A handle substrate of a composite wafer for a semiconductor: said handle substrate comprising a polycrystalline ceramic sintered body; wherein said handle substrate comprises an outer peripheral portion comprising a notch; and wherein said notch comprises an as-sintered surface. 2 . The handle substrate of claim 1 , wherein said as-sintered surface has a surface roughness Ra of 0.5 μm or lower. 3 . The handle substrate of claim 1 , wherein s…
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Electricity · mapped topic
Electricity · mapped topic
- H10P72/70Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US2015357221A1 cover?
- In a handle substrate for a composite wafer for a semiconductor, particles from the wafer with a notch formed therein are reduced. The handle substrate 1 A or 1 B for the composite wafer for the semiconductor is formed of a polycrystalline ceramic sintered body, and includes a notch 2 A or 2 B in its outer peripheral portion. The notch is formed with an as-sintered surface.
- Who is the assignee on this patent?
- Ngk Insulators Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P72/70. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Dec 10 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).