Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
US9754815B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9754815-B2 |
| Application number | US-201415025830-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 29, 2014 |
| Priority date | Sep 30, 2013 |
| Publication date | Sep 5, 2017 |
| Grant date | Sep 5, 2017 |
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A composite substrate 1 according to the present invention comprises: a supporting substrate 10 that is formed of an insulating material; a semiconductor part 20 that is disposed over the supporting substrate 10 ; and interfacial inclusions 30 that are present at the interface between the supporting substrate 10 and the semiconductor part 20 and contains Ni and Fe so that the ratio of Ni to Fe is 0.4 or more. Consequently, the present invention is able to provide a highly reliable composite substrate wherein the interfacial inclusions 30 are prevented from diffusing into the semiconductor part 20.
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The invention claimed is: 1. A composite substrate comprising: a supporting substrate comprising a single crystal of an insulating material; a silicon semiconductor portion on the supporting substrate; and interfacial inclusions present in a density of 10 12 atoms/cm 2 or less and located at an interface between the supporting substrate and the silicon semiconductor portion, the interfacial inclusions containing Ni and Fe, and the ratio of Ni to Fe being 0.4 or more. 2. The composite substrate according to claim 1 , wherein the interfacial inclusions contain Ni and Fe, and the ratio of Ni to Fe is 1 or more. 3. The composite substrate according to claim 1 , wherein the support substrate is formed of one selected from lithium tantalate, silicon carbide, and sapphire. 4. A method for producing a composite substrate, comprising: a preparation step of preparing a supporting substrate comprising a single crystal of an insulating material and a single-crystal silicon semiconductor substrate; an activation step of individually irradiating a main surface of the supporting substrate and a main surface of the silicon semiconductor substrate using a fast atom beam (FAB) gun to activate both of the main surfaces with the silicon the semiconductor substrate and the supporting substrate not facing each other to form an activated main surface of the silicon semiconductor substrate and an activated main surface of the supporting substrate; a metal supply step of supplying a metal containing Ni and Fe to at least one of the activated main surface of the supporting substrate and the activated main surface of the silicon semiconductor substrate, the metal being composed of a metal element other than main components contained in the supporting substrate and the silicon semiconductor substrate; a bonding step of bringing the activated main surface of the silicon semiconductor substrate and the activated main surface of the supporting substrate into contact with each other at normal temperature to bond the silicon semiconductor substrate and the supporting substrate together; and a thickness reduction step of reducing the thickness of the silicon semiconductor substrate from the other main surface of the silicon semiconductor substrate to form the silicon semiconductor substrate to a silicon semiconductor portion to form a composite substrate comprising a supporting substrate comprising a single crystal of an insulating material, a silicon semiconductor portion on the supporting substrate, and interfacial inclusions located at an interface between the supporting substrate and the silicon semiconductor portion in a density of 10 12 atoms/cm 2 or less, the interfacial inclusions containing Ni and Fe, and the ratio of Ni to Fe being 0.4 or more. 5. The method for producing a composite substrate according to claim 4 , wherein the activation step and the metal supply step are simultaneously performed. 6. The method for producing a composite substrate according to claim 4 , wherein the activation step includes: a first activation substep of activating the silicon semiconductor substrate using the FAB gun in a state in which the silicon semiconductor substrate does not face the supporting substrate, and a second activation substep of activating the supporting substrate by irradiation using the FAB gun under a condition ln which cumulative irradiation energy is lower than that of irradiation using the FAB gun ln the first activation substep. 7. The method for producing a composite substrate according to claim 6 , further comprising, after the first activation substep and before the bonding step, an additional irradiation step of subjecting the silicon semiconductor substrate to irradiation using the FAB gun under a condition in which cumulative irradiation energy is lower than that of the irradiation using the FAB gun ln the first activation substep.
Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title
using bonding · CPC title
Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating · CPC title
Electricity · mapped topic
Electricity · mapped topic
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