Two-level system main memory

Patent metadata

Field	Value
Publication number	US-9087584-B2
Application number	US-201314105708-A
Country	US
Kind code	B2
Filing date	Dec 13, 2013
Priority date	Dec 22, 2010
Publication date	Jul 21, 2015
Grant date	Jul 21, 2015

Abstract

Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.
The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

First claim

The invention claimed is:

1. A system comprising:
system main memory, the system main memory including a first memory level of volatile memory and a second memory level comprising non-volatile memory, the first memory level being a near memory comprising one or more Dynamic Random Access Memory (DRAM) devices and the first memory level to include a cached subset of the second memory level, the second memory level being a far memory that is larger and slower in comparison with the near memory, wherein the system main memory is to be communicatively coupled to a processor separate from the system main memory, and wherein a size of the system main memory to be presented to an operating system (OS) is a size of the second memory level; and
a two-level memory (2LM) controller to transfer data between the second memory level and the first memory level of the system main memory and the processor based on one or more OS requests.

2. The system of claim 1 , further comprising:
disk storage memory.

3. The system of claim 2 , wherein the far memory is to include a cached subset of the disk storage memory.

4. The system of claim 2 , wherein the second memory level and the disk storage memory are included in a memory subsystem comprising at least one nonvolatile memory device and control logic, and the system further comprises:
a second memory level controller to partition the memory subsystem into two or more partitions including a memory partition comprising the second memory level and a disk storage memory partition.

5. The system of claim 4 , wherein the at least one nonvolatile memory device of the memory subsystem is included in a solid state drive (SSD).

6. The system of claim 1 , wherein the non-volatile memory of the second memory level comprises phase change memory.

7. The system of claim 1 , wherein the 2LM controller is included in the processor.

8. The system of claim 1 , wherein the 2LM controller, in response to a detected uncorrectable error in a data segment included in the first memory level, is to further:
determine if the data segment is unmodified with respect to a corresponding data segment included in the second memory level;
copy the corresponding data segment included in the second memory level to the first memory level in response to a determination that the data segment is unmodified; and
report a system error if the data segment is modified.

9. The system of claim 8 , wherein the 2LM controller, in response to a detected uncorrectable error in the corresponding data segment included in the second memory level, is to further report a system error.

10. The system of claim 1 , wherein the first memory level is coupled with the processor by a first means and the second memory level is coupled with the processor by a second means, the first means having higher bandwidth and lower latency in comparison with the second means.

11. The system of claim 1 , wherein the OS and system applications are unaware of the first memory level.

12. The system of claim 1 , wherein the near memory is a transparent cache of the far memory.

13. The system of claim 1 , further comprising:
a near memory controller to manage near memory; and
a far memory controller to manage far memory.

14. The system of claim 1 , wherein the 2LM controller is to fetch a data segment from far memory and to write the data segment to near memory upon a determination that the data segment is not in near memory.

15. A two-level memory (2LM) controller comprising:
a bus to communicatively couple the 2LM controller to a processor;
logic to determine if a data operand of a request received from the processor is stored in a first memory level of a main memory separate from the processor, wherein the first memory level of the main memory is to comprise one or more Dynamic Random Access Memory (DRAM) devices and is to include a cached subset of a second memory level of the main memory, the first memory level being a near memory and the second memory level being a far memory that is larger and slower in comparison with the near memory; and
logic to retrieve the data operand from the second memory level of the main memory, the second level comprising a non-volatile memory, in response to a determination that the requested data operand is not stored in the first memory level of the main memory.

16. The 2LM controller of claim 15 , further comprising:
logic to write the retrieved data operand from the second memory level of the main memory to the first memory level of the main memory.

17. The 2LM controller of claim 15 , wherein the 2LM controller is included in a processor package including the processor.

18. The 2LM controller of claim 15 , further comprising:
logic to report a system error in response to a detected uncorrectable error in a data segment included in the second memory level of the main memory.

19. A method comprising:
presenting a size of a system main memory, the system main memory comprising a first memory level and a second memory level, the second memory level comprising non-volatile memory, to an operating system (OS) as a size of the second memory level, wherein the first memory level comprises one or more Dynamic Random Access Memory (DRAM) devices and includes a cached subset of the second memory level, and wherein the system main memory is communicatively coupled to a processor separate from the system main memory, wherein the first memory level is a near memory and the second memory level is a far memory that is larger and slower in comparison with the near memory; and
transferring data between the second memory level and the first memory level of the system main memory and the processor based on one or more OS requests.

20. The method of claim 19 , wherein the second memory level is to store a cached subset of disk storage memory.

21. The method of claim 20 , wherein the second memory level and the disk storage memory are included in a memory subsystem comprising at least one nonvolatile memory device and control logic, and the method further comprises:
partitioning the memory subsystem into two or more partitions including a memory partition comprising the second memory level and a disk storage memory partition.

22. The method of claim 21 , wherein the at least one nonvolatile memory device of the memory subsystem is included in a solid state drive (SSD).

23. The method of claim 19 , wherein the non-volatile memory of the second memory level comprises phase change memory.

24. The method of claim 19 , further comprising:
in response to detecting an uncorrectable error in a data segment included in the first memory level:
determining if the data segment is unmodified with respect to a corresponding data segment included in the second memory level;
copying the corresponding data segment included in the second memory level to the first memory level in response to determining that the data segment is unmodified; and
reporting a system error if the data segment is modified.

25. The method of claim 24 , further comprising:
reporting a system error in response to detecting an uncorrectable error in the corresponding data segment included in the second memory level.

26. The method of claim 19 , wherein the near memory is a transparent cache of the far memory.

27. The method of claim 19 , wherein a system including the system main memory further includes:
a near memory

Assignees

• Intel Corp

Inventors

• Dahlen Eric J
• Hinton Glenn J
• Ramanujan Raj K

Classifications

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G06F12/0893

  Caches characterised by their organisation or structure · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F11/0766

  Error or fault reporting or storing · CPC title

• G11C14/009 Primary

  and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material · CPC title