Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

Patent metadata

Field	Value
Publication number	US-9418009-B2
Application number	US-201314142045-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Dec 27, 2013
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.

First claim

We claim:

1. A processor comprising:
one or more processing cores;
a memory controller to interface with a system memory having a near memory and a far memory; and
logic circuitry to track state information of a cache line, said state information including a selected one of an inclusive state and a non-inclusive state, said inclusive state indicating that a copy of said cache line exists in near memory, said non-inclusive state indicating that a copy of said cache line does not exist in said near memory, said logic circuitry to cause said memory controller to determine whether a write request is generated remotely or generated locally, and
when the write request is generated remotely, to instruct the memory controller to perform a read of the near memory before performing a write to a cache line targeted by the write request,
when the write request is generated locally and the cache line targeted by the write request is in the inclusive state, to instruct the memory controller to perform a write to the cache line targeted by the write request without performing a read of the near memory, and
when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state, to instruct the memory controller to perform a read of the near memory before performing a write to the cache line targeted by the write request.

2. The processor of claim 1 further comprising a plurality of caching levels above the memory controller, and wherein said logic circuitry is part of a cache home agent.

3. The processor of claim 2 wherein said cache home agent includes snoop filter circuitry to track inclusive and non-inclusive state information of cache lines cached above a last caching level of said processor.

4. The processor of claim 3 wherein said cache home agent includes a last caching level of said processor.

5. The processor of claim 2 wherein said plurality of caching levels include a distributed last caching level, a snoop-filter (SF), and a cache home agent (CHA).

6. The processor of claim 5 wherein said processing cores include respective hashing functions to direct all system memory addresses that map to a same near memory entry to a same last level cache slice.

7. The processor of claim 1 wherein said logic circuitry is to identify when a read request for a cache line having a system memory address that is different than said cache line but that still maps to a same near memory entry where a copy of said cache line resides, and, if said cache line is in an inclusive state, change said cache line's state to non-inclusive in response.

8. The processor of claim 7 wherein said logic circuitry marks all other cached cache lines that map to said same near memory entry as non-inclusive.

9. The processor of claim 1 wherein said logic circuitry is to cause said memory controller to perform a read of the near memory for all read requests to the system memory.

10. A method comprising:
instructing a memory controller of a processor to read a cache line from a system memory having a near memory and a far memory;
marking said cache line as one of an inclusive state and a non-inclusive state, said inclusive state indicating that a copy of said cache line exists in near memory, said non-inclusive state indicating that a copy of said cache line does not exist in said near memory;
determining whether a write request for said cache line is generated remotely or generated locally;
performing a read of the near memory before performing a write to a cache line targeted by the write request when the write request is generated remotely;
performing a write to the cache line targeted by the write request without performing a read of the near memory when the write request is generated locally and the cache line targeted by the write request is in the inclusive state; and performing a read of the near memory before performing a write to the cache line targeted by the write request when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state.

11. The method of claim 10 further comprising recognizing that a read request for a second cache line has targeted said system memory, recognizing that said second cache line has a system memory address that is different than said cache line's system memory address, and recognizing that said system memory address of said second cache line maps to a same entry in said near memory where a copy of said cache line resides, and changing a state of said cache line to a non-inclusive state in response.

12. The method of claim 11 further comprising marking said second cache line as having an inclusive state.

13. The method of claim 12 further comprising marking all other cache lines that are cached in said processor and have a system memory address that maps to said same entry as having a non-inclusive state.

14. The method of claim 10 further comprising recognizing that a second read request for said cache line has targeted said system memory, and keeping a state of said cache line in the inclusive state in response.

15. The method of claim 10 further comprising receiving a remotely generated write request at said processor and instructing said memory controller to satisfy said remotely generated write request by performing a read of near memory before performing a write into said system memory.

16. A computing system comprising:
a system memory having a near memory and a far memory;
a processor comprising one or more processing cores;
a memory controller to interface with said system memory; and
logic circuitry to track state information of a cache line, said state information including a selected one of an inclusive state and a non-inclusive state, said inclusive state indicating that a copy of said cache line exists in near memory, said non-inclusive state indicating that a copy of said cache line does not exist in said near memory, said logic circuitry to cause said memory controller to determine whether a write request is generated remotely or generated locally, and
when the write request is generated remotely, to instruct the memory controller to perform a read of the near memory before performing a write to a cache line targeted by the write request,
when the write request is generated locally and the cache line targeted by the write request is in the inclusive state, to instruct the memory controller to perform a write to the cache line targeted by the write request without performing a read of the near memory, and
when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state, to instruct the memory controller to perform a read of the near memory before performing a write to the cache line targeted by the write request.

17. The computing system of claim 16 further comprising a plurality of caching levels comprising a distributed last caching level and wherein said processing cores include respective hashing functions to direct all system memory addresses that map to a same near memory entry to a same last level cache slice.

18. The computing system of claim 16 wherein said logic circuitry is to identify when a read request for said cache line having a system memory address that is different than said cache line but that still maps to a same near memory entry where a copy of said cache line resides, and, if said cache line is in an inclusive state, change said cache line's state to non-inclusive in response.

19. The computing system of claim 18 wh

Assignees

• Intel Corp

Inventors

• Moga Adrian C
• Geetha Vedaraman
• Fahim Bahaa
• Blankenship Robert G
• Liu Yen-Cheng
• Chamberlain Jeffrey D
• Van Doren Stephen R

Classifications

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title