Insulated gate bipolar transistor failure mode detection and protection system and method

Patent metadata

Field	Value
Publication number	US-9726712-B2
Application number	US-201414284895-A
Country	US
Kind code	B2
Filing date	May 22, 2014
Priority date	Jun 13, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An assembly including an insulated gate bipolar transistor (IGBT) is provided. The IGBT is coupled with a gate driver for receiving a gating signal to drive the IGBT and providing a feedback signal of the IGBT which indicates a change of a collector-emitter voltage of the IGBT. The assembly further includes a failure mode detection unit for determining whether the IGBT is faulted based on a timing sequence of the gating signal and feedback signal. The failure mode detection unit is capable of differentiating fault types including a gate driver fault, a failed turn-on fault, a short-circuit fault, a turn-on over-voltage fault and a turn-off over-voltage fault. Accordingly, an IGBT failure mode detection method is also provided.

First claim

The invention claimed is:

1. An assembly comprising:
an insulated gate bipolar transistor (IGBT), having a first IGBT coupled with a first gate driver for receiving a gating signal to drive the IGBT and providing a feedback signal of the IGBT which indicates a change of a collector-emitter voltage of the IGBT;
at least one additional IGBT having an additional second IGBT coupled with at least one additional second gate driver, wherein the first and additional IGBTs are series connected;
a first failure mode detection unit for determining whether the first IGBT is faulted, and differentiating fault types including a first gate driver fault, failed turn-on fault, a short-circuit fault, a turn-on over-voltage fault and a turn-off over-voltage fault, based on a timing sequence of the gating signal and the feedback signal;
at least one second failure mode detection unit for determining whether the second IGBT is faulted, and differentiating fault types including a second gate driver fault, failed turn-on fault, a short-circuit fault, a turn-on over-voltage fault and a turn-off over-voltage fault, based on a timing sequence of the gating signal and the feedback signal; and
a central controller programmed to send an isolation signal for isolating the faulted IGBT or IGBTs from its gate driver or their gate drivers if the number of faulted IGBTs is less than or equal to the number of redundant IGBTs,
wherein the first and additional IGBTs comprise a number of redundant IGBTs, and there is a switch device between each IGBT and its gate driver.

2. The assembly of claim 1 , wherein the central controller is programmed to shut down the gating signal or isolate the IGBT if the IGBT is faulted.

3. The assembly of claim 1 , wherein the central controller is programmed to shut down the gating signals if the number of faulted IGBTs is greater than the number of redundant IGBTs.

4. The assembly of claim 1 , wherein the failure mode detection unit is programmed to:
compare:
(a) an interval t 1 between a rising edge of the gating signal and a rising edge of a first feedback signal pulse that immediately follows the rising edge of the gating signal, with a maximum turn-on ack-wait time T 1 ;
(b) a duration t 2 of the first feedback signal pulse, with a maximum turn-on ack time T 2 ;
(c) an interval t 3 between a falling edge of the first feedback signal pulse and a rising edge of a second feedback signal pulse that immediately follows the first feedback signal pulse, with a short-circuit blanking time T 3-1 and an over-voltage blanking time T 3-2 ;
(d) a duration t 4 of the second feedback signal pulse, with a maximum over-voltage time T 4 ;
(e) an interval t 5 between a falling edge of the gating signal and a rising edge of a third feedback signal pulse that immediately follows the falling edge of the gating signal pulse, with a maximum turn-off ack-wait time T 5 ; and
(f) a duration t 6 of the third feedback signal pulse, with a maximum turn-off ack time T 6 ; and
diagnose that:
a gate driver fault occurs if t 1 >T 1 ;
a failed turn-on fault occurs to the IGBT if t 1 <T 1 or t 2 >T 2 ;
a short-circuit fault occurs to the IGBT if t 1 ≦T 1 , t 2 ≦T 2 and T 3-2 ≦t 3 ≦T 3-1 ;
a turn-on over-voltage fault occurs to the IGBT if t 1 ≦T 1 , t 2 ≦T 2 , t 3 ≦T 3-2 and t 4 ≧T 4 ;
a turn-off over-voltage fault occurs to the IGBT if t 5 >T 5 and t 6 >T 6 .

5. The assembly of claim 4 , wherein T 1 , T 2 , T 3-1 , T 3-2 , T 4 , T 5 , and T 6 . are approximately 160 ns, 800 ns, 6 μs, 500 ns, 800 ns, 550 ns and 1 μs, respectively.

6. An insulated gate bipolar transistor (IGBT) failure mode detection method, comprising:
obtaining a gating signal to drive one or more series connected IGBTs;
obtaining a feedback signal of each IGBT, which indicates a change of a collector-emitter voltage of the IGBT;
comparing a timing sequence of the gating signal and feedback signal of each IGBT with a reference timing sequence to determine whether the IGBT is faulted and, if the IGBT is faulted, to differentiate fault types including a gate driver fault, a failed turn-on fault, a short-circuit fault, a turn-on over-voltage fault and a turn-off over-voltage fault; and
isolating, if the one or more series connected IGBTs comprise a number of redundant IGBTs, the faulted IGBT or IGBTs from its gate driver or their gate drivers if the number of faulted IGBTs is less than or equal to the number of redundant IGBTs.

7. The method of claim 6 , further comprising shutting down the gating signals to all the IGBTs if the number of faulted IGBTs is greater than the number of redundant IGBTs.

8. The method of claim 6 , wherein the step of determining whether the IGBT is faulted and differentiating the fault type comprises:
comparing:
(a) an interval t 1 between a rising edge of a first gating signal pulse and a rising edge of a first feedback signal pulse that immediately follows the rising edge of the gating signal pulse, with a maximum turn-on ack-wait time T 1 ;
(b) duration t 2 of the first feedback signal pulse, with a maximum turn-on ack time T 2 ;
(c) an interval t 3 between a falling edge of the first feedback signal pulse and a rising edge of a second feedback signal pulse that immediately follows the first feedback signal pulse, with a short-circuit blanking time T 3-1 and an over-voltage blanking time T 3-2 ;
(d) duration t 4 of the second feedback signal pulse, with a maximum over-voltage time T 4 ;
(e) an interval t 5 between a falling edge of the first gating signal pulse or a second gating signal pulse and a rising edge of a third feedback signal pulse that immediately follows the falling edge of the first or second gating signal pulse, with a maximum turn-off ack-wait time T 5 ; and
(f) duration t 6 of third feedback signal pulse, with a maximum turn-off ack time T 6 ; and
diagnosing that:
a gate driver fault occurs if t 1 >T 1 ;
a failed turn-on fault occurs to the IGBT if t 1 ≦T 1 and t 2 >T 2 ;
a short-circuit fault occurs to the IGBT if t 1 ≦T 1 , t 2 ≦T 2 and T 3-2 ≦t 3 ≦T 3-1 ;
a turn-on over-voltage fault occurs to the IGBT if t 1 ≦T 1 , t 2 ≦T 2 , t 3 ≦T 3-2 and t 4 ≧T 4 ;
a turn-off over-voltage fault occurs to the IGBT if t 5 >T 5 and t 6 >T 6 .

9. The method of claim 8 , wherein T 1 , T 2 , T 3-1 , T 3-2 , T 4 , T 5 , and T 6 are approximately 160 ns, 800 ns, 6 μs, 500 ns, 800 ns, 550 ns and 1 μs, respectively.

10. An assembly comprising:
insulated gate bipolar transistors (IGBTs) connected in series, each IGBT having a gate driver for receiving a gating signal to drive the IGBT and providing a feedback signal of the IGBT which indicates a change of a collector-emitter voltage of the IGBT, and a failure mode detection unit for determining whether the IGBT is faulted, and differentiating fault types based on a timing sequence of the gating signal and the feedback signal; and
a central controller programmed to send an isolation signal for isolating the faulted IGBT or IGBTs from its gate driver or their gate drivers if the number of faulted IGBTs is less than or equal to the number of redundant IGBTs.

11. The assembly of claim 10 , wherein the central controller is programmed to shut down the gating signal or isolate the IGBT if the IGBT is faulted.

12. The assembly of claim 10 , wherein the central controller is programmed to shut down the gating signals if the number of faulted IGBTs is greater than the number of redundant IGBTs.

13. The assembly of claim 10 , wherein the failure mode detection unit is programmed to:
compare:
(a) an interval t 1 between a rising edge of the gating signal and a rising edge of a first feedbac

Assignees

• Gen Electric

Inventors

• Wu Tao

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• G01R31/2612 Primary

  for measuring frequency response characteristics, e.g. cut-off frequency thereof · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H03K17/10

  Modifications for increasing the maximum permissible switched voltage · CPC title

• H03K17/18

  Modifications for indicating state of switch · CPC title