Photoresist film placing method, semiconductor device manufacturing method, electro-optical device, and electronic device
US-2015294859-A1 · Oct 15, 2015 · US
US9426895B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9426895-B2 |
| Application number | US-201514836989-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 27, 2015 |
| Priority date | Jan 5, 2015 |
| Publication date | Aug 23, 2016 |
| Grant date | Aug 23, 2016 |
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A method of manufacturing a touch screen panel, including forming first and second conductive layers and an organic insulating layer on a substrate; forming a first organic insulating pattern having a first thickness and a second organic insulating pattern having a second thickness, the second thickness being larger than the first thickness; forming first and second conductive patterns; exposing a part of the second conductive pattern to form a third organic insulating pattern having a thickness smaller than the second thickness; removing the exposed second conductive pattern; forming an organic insulating capping layer surrounding the first and second conductive patterns positioned under the third organic insulating pattern; and forming a third conductive layer on the first conductive pattern and the organic insulating capping layer, the first conductive pattern being exposed, and then forming a connection pattern electrically connected with the exposed first conductive pattern using a second mask.
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a touch screen panel, comprising: forming a first conductive layer, a second conductive layer, and an organic insulating layer on a substrate; forming a first organic insulating pattern having a first thickness and a second organic insulating pattern having a second thickness by disposing a first mask on the organic insulating layer, the second thickness being larger than the first thickness; forming first and second conductive patterns by etching the first and second conductive layers at exposed portions using the first and second organic insulating patterns as masks; exposing a part of the second conductive pattern by ashing the first organic insulating pattern and ashing the second organic insulating pattern to form a third organic insulating pattern having a thickness smaller than the second thickness; removing the exposed part of the second conductive pattern by etching and exposing the first conductive pattern positioned under the second conductive pattern; forming an organic insulating capping layer surrounding the first and second conductive patterns positioned under the third organic insulating pattern by thermally curing the third organic insulating pattern; and forming a third conductive layer on the first conductive pattern and the organic insulating capping layer, the first conductive pattern being exposed, and then forming a connection pattern electrically connected with the exposed first conductive pattern using a second mask. 2. The method as claimed in claim 1 , wherein the first conductive layer includes a transparent material. 3. The method as claimed in claim 2 , wherein the transparent material includes one or more of an indium tin oxide (ITO), a silver nano wire (AgNW), or a conductive polymer. 4. The method as claimed in claim 1 , wherein the second conductive layer includes a material having a lower resistance value than that of the first conductive layer. 5. The method as claimed in claim 4 , wherein the material having the lower resistance value includes one or more of molybdenum (Mo), silver (Ag), titanium (Ti), aluminum (Al), or copper (Cu). 6. The method as claimed in claim 1 , wherein the organic insulating layer includes a material having thermal flow. 7. The method as claimed in claim 1 , wherein the first mask includes a half-tone mask. 8. The method as claimed in claim 1 , wherein the etching includes wet etching. 9. The method as claimed in claim 1 , wherein removing the exposed part of the second conductive pattern by etching and exposing the first conductive pattern positioned under the second conductive pattern includes over-etching a lateral surface of the second conductive pattern positioned under the third organic insulating pattern. 10. The method as claimed in claim 9 , wherein a width of the second conductive pattern is smaller than a width of the third organic insulating pattern. 11. The method as claimed in claim 1 , wherein the connection pattern is on the organic insulating capping layer. 12. The method as claimed in claim 11 , wherein the connection pattern includes a transparent conductive material. 13. The method as claimed in claim 1 , wherein forming the first and second conductive patterns by etching the first and second conductive layers at the exposed portions using the first and second organic insulating patterns as masks includes forming a connection part crossing the connection pattern and integrally formed with the second conductive pattern.
Digitisers structurally integrated in a display · CPC title
After-treatment, e.g. cleaning or desmearing of holes · CPC title
Etching masks · CPC title
Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title
Stripping a part of an upper metal layer to expose a lower metal layer, e.g. by etching or using a laser · CPC title
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