Thin film transistor, method for fabricating the same and display apparatus

Patent metadata

Field	Value
Publication number	US-9711653-B2
Application number	US-201414409333-A
Country	US
Kind code	B2
Filing date	Jun 20, 2014
Priority date	Oct 11, 2013
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Embodiments of the present invention provide a thin film transistor, method for fabricating the thin film transistor and display apparatus. The method includes steps of: forming an active layer pattern which has a mobility greater than a predetermined threshold from an active layer material; and performing ion implantation on the active layer pattern. The energy of a compound bond formed from the implanted ions is greater than that of a compound bond formed from ions in the active layer material, thereby reducing the chance of vacancy formation and reducing the carrier concentration. Therefore, the mobility of the active layer surface is reduced, the leakage current is reduced, the threshold voltage is adjusted to shift toward positive direction and performance of the thin film transistor is improved.

First claim

What is claimed is:

1. A method for fabricating a thin film transistor, comprising:
forming an active layer pattern from zinc oxynitride; and
implanting Ga or Al ions into a top portion of a channel region of the active layer pattern so as to convert the channel region of the active layer pattern to a top layer of zinc oxynitride doped with Ga or Al ions and a bottom layer of zinc oxynitride, such that in the thin film transistor, a mobility of the top layer is less than a mobility of the bottom layer,
wherein before the implanting, the method further comprises:
forming an etch stop layer pattern on the active layer pattern, and
forming a source/drain pattern on both the etch stop layer pattern and the active layer pattern.

2. The method according to claim 1 , wherein before the implanting, the method further comprises:
forming a protection layer on both the etch stop layer pattern and the source/drain pattern.

3. The method according to claim 2 , wherein the protection layer is a laminated layer of SiOx and SiNx.

4. The method according to claim 1 , wherein before the forming the active layer pattern, the method further comprises:
forming a gate pattern on a substrate; and
forming a gate insulating layer on both the gate pattern and the substrate,
wherein the active layer pattern is formed on the gate insulating layer.

5. The method according to claim 2 , wherein before the forming the active layer pattern, the method further comprises:
forming a gate pattern on a substrate; and
forming a gate insulating layer on both the gate pattern and the substrate,
wherein the active layer pattern is formed on the gate insulating layer.

6. The method according to claim 3 , wherein before the forming the active layer pattern, the method further comprises:
forming a gate pattern on a substrate; and
forming a gate insulating layer on both the gate pattern and the substrate,
wherein the active layer pattern is formed on the gate insulating layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Meili
• Jiang Chunsheng
• Wang Dongfang
• Liu Fengjuan

Classifications

• H10P30/22

  using masks · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H01L21/266

  Electricity · mapped topic