Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9218966-B2
Application number	US-201213649486-A
Country	US
Kind code	B2
Filing date	Oct 11, 2012
Priority date	Oct 14, 2011
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

To suppress a decrease in on-state current in a semiconductor device including an oxide semiconductor. Provided is a semiconductor device including the following: an oxide semiconductor film which serves as a semiconductor layer; a gate insulating film including an oxide containing silicon, over the oxide semiconductor film; a gate electrode which overlaps with at least the oxide semiconductor film, over the gate insulating film; and a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film. In the semiconductor device, the oxide semiconductor film overlapping with at least the gate electrode includes a region in which a concentration of silicon distributed from the interface with the gate insulating film toward the inside of the oxide semiconductor film is lower than or equal to 1.1 at. %.

First claim

What is claimed is:

1. A semiconductor device comprising:
a layer over a substrate, the layer comprising an insulating film, a first conductive film and a second conductive film;
an In—Zn—Ga-based oxide semiconductor film over each of the insulating film, the first conductive film and the second conductive film, the In—Zn—Ga-based oxide semiconductor film comprising a first portion which has crystallinity;
a source electrode and a drain electrode over the In—Zn—Ga-based oxide semiconductor film;
a gate insulating film over the In—Zn—Ga-based oxide semiconductor film, the gate insulating film comprising an oxide comprising silicon; and
a gate electrode over the gate insulating film, the gate electrode overlapping the In—Zn—Ga-based oxide semiconductor film,
wherein the source electrode and the first conductive film overlap each other,
wherein the drain electrode and the second conductive film overlap each other,
wherein each of the source electrode, the drain electrode, the first conductive film and the second conductive film is electrically connected to the In—Zn—Ga-based oxide semiconductor film,
wherein the In—Zn—Ga-based oxide semiconductor film comprises a first region in which a concentration of silicon distributed from an interface with the gate insulating film toward an inside of the In—Zn—Ga-based oxide semiconductor film is lower than or equal to 1.1 at. %,
wherein the In—Zn—Ga-based oxide semiconductor film further comprises a second region under the first region, and
wherein a concentration of silicon contained in the second region is lower than the concentration of silicon contained in the first region.

2. The semiconductor device according to claim 1 ,
wherein the first region is in contact with the gate insulating film and has a thickness less than or equal to 5 nm.

3. The semiconductor device according to claim 1 ,
wherein the concentration of silicon contained in the first region is lower than or equal to 0.83 at. %.

4. The semiconductor device according to claim 1 ,
wherein the concentration of silicon contained in the first region is lower than or equal to 0.1 at. %.

5. The semiconductor device according to claim 1 ,
wherein the gate insulating film contains carbon, and
wherein a concentration of carbon in the first region is lower than or equal to 1.0×10 20 atoms/cm 3 .

6. The semiconductor device according to claim 1 ,
wherein the In—Zn—Ga-based oxide semiconductor film comprises a second portion which has an amorphous structure.

7. The semiconductor device according to claim 1 ,
wherein the In—Zn—Ga-based oxide semiconductor film comprises a third portion, and
wherein a c-axis of the third portion is aligned in a direction parallel to a normal vector of a surface of the In—Zn—Ga-based oxide semiconductor film.

8. The semiconductor device according to claim 1 ,
wherein a surface of the first conductive film is approximately the same in height from the substrate as a surface of the insulating film.

9. The semiconductor device according to claim 1 ,
wherein the In—Zn—Ga-based oxide semiconductor film comprises a third region and a fourth region,
wherein the third region has lower resistance than the fourth region, and
wherein the third region, the source electrode and the first conductive film overlap one another.

10. A semiconductor device comprising:
a layer over a substrate, the layer comprising an insulating film, a first conductive film and a second conductive film;
an oxide semiconductor film comprising In, Ga and Zn as its main components, the oxide semiconductor film over each of the insulating film, the first conductive film and the second conductive film, wherein the oxide semiconductor film comprises a first portion which has crystallinity;
a source electrode and a drain electrode over the oxide semiconductor film;
a gate insulating film in contact with the oxide semiconductor film, the gate insulating film comprising an oxide comprising silicon; and
a gate electrode in contact with the gate insulating film,
wherein the gate electrode and the oxide semiconductor film overlap each other,
wherein the gate insulating film is provided between the oxide semiconductor film and the gate electrode,
wherein the source electrode and the first conductive film overlap each other,
wherein the drain electrode and the second conductive film overlap each other,
wherein each of the source electrode, the drain electrode, the first conductive film and the second conductive film is electrically connected to the oxide semiconductor film,
wherein the oxide semiconductor film comprises a first region in which a concentration of silicon distributed from an interface with the gate insulating film toward an inside of the oxide semiconductor film is lower than or equal to 1.1 at. %,
wherein the oxide semiconductor film further comprises a second region,
wherein a concentration of silicon contained in the second region is lower than the concentration of silicon contained in the first region, and
wherein the first region is provided between the second region and the gate insulating film.

11. The semiconductor device according to claim 10 ,
wherein the first region is in contact with the gate insulating film and has a thickness less than or equal to 5 nm.

12. The semiconductor device according to claim 10 ,
wherein the concentration of silicon contained in the first region is lower than or equal to 0.83 at. %.

13. The semiconductor device according to claim 10 ,
wherein the concentration of silicon contained in the first region is lower than or equal to 0.1 at. %.

14. The semiconductor device according to claim 10 ,
wherein the gate insulating film contains carbon, and
wherein a concentration of carbon in the first region is lower than or equal to 1.0×10 20 atoms/cm 3 .

15. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor film comprises a second portion which has an amorphous structure.

16. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor film comprises a third portion, and
wherein a c-axis of the third portion is aligned in a direction parallel to a normal vector of a surface of the oxide semiconductor film.

17. The semiconductor device according to claim 10 ,
wherein a surface of the first conductive film is approximately the same in height from the substrate as a surface of the insulating film.

18. The semiconductor device according to claim 10 ,
wherein the oxide semiconductor film comprises a third region and a fourth region,
wherein the third region has lower resistance than the fourth region, and
wherein the third region, the source electrode and the first conductive film overlap one another.

Assignees

• Semiconductor Energy Lab

Inventors

• Honda Tatsuya
• Tsubuku Masashi
• Nonaka Yusuke
• Yamazaki Shunpei

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/22 Primary

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title