Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9240488-B2
Application number	US-96833810-A
Country	US
Kind code	B2
Filing date	Dec 15, 2010
Priority date	Dec 18, 2009
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A transistor including an oxide semiconductor, which has good on-state characteristics, and a high-performance semiconductor device including a transistor capable of high-speed response and high-speed operation. In the transistor including an oxide semiconductor, oxygen-defect-inducing factors are introduced (added) into an oxide semiconductor layer, whereby the resistance of a source and drain regions are selectively reduced. Oxygen-defect-inducing factors are introduced into the oxide semiconductor layer, whereby oxygen defects serving as donors can be effectively formed in the oxide semiconductor layer. The introduced oxygen-defect-inducing factors are one or more selected from titanium, tungsten, and molybdenum, and are introduced by an ion implantation method.

First claim

The invention claimed is:

1. A semiconductor device comprising:
an oxide semiconductor layer including a channel formation region, a first region, and a second region over a substrate;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer;
an insulating layer over the gate electrode layer and the gate insulating layer; and
a source electrode layer and a drain electrode layer over the insulating layer,
wherein the first region is one of a source or drain region,
wherein each of the first region and the second region includes oxygen defects due to oxygen-defect-inducing factors,
wherein the second region is between the channel formation region and the first region,
wherein a concentration of the oxygen-defect-inducing factors of the second region is lower than that of the first region,
wherein the insulating layer includes a first part overlapping with the first region and a second part overlapping with the second region,
wherein an interface between the first part and the second part is substantially aligned with an interface between the first region and the second region, and
wherein the gate insulating film is over and in contact with the first region and the second region.

2. The semiconductor device according to claim 1 ,
wherein the channel formation region includes oxygen-defect-inducing factors.

3. The semiconductor device according to claim 2 ,
wherein a concentration of the oxygen-defect-inducing factors in the channel formation region is less than 1×10 14 atoms/cm 3 .

4. The semiconductor device according to claim 1 ,
wherein the gate electrode overlaps with the channel formation region,
wherein the insulating layer covers the oxide semiconductor layer, the gate insulating layer, and the gate electrode layer, and
wherein the source electrode layer is electrically connected to the source region and the drain electrode layer is electrically connected to the drain region.

5. The semiconductor device according to claim 1 , wherein the oxygen-defect-inducing factors are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

6. The semiconductor device according to claim 1 ,
wherein the channel formation region has n-type conductivity.

7. A semiconductor device comprising:
an oxide semiconductor layer including a channel formation region, a first region, and a second region over a substrate;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer;
an insulating layer over the oxide semiconductor layer, the insulating layer having a first surface and a second surface opposing to the first surface; and
a source electrode layer and a drain electrode layer over the insulating layer,
wherein the first region is one of a source or drain region,
wherein each of the first region and the second region includes oxygen defects due to oxygen-defect-inducing factors,
wherein the second region is between the channel formation region and the first region,
wherein a concentration of the oxygen-defect-inducing factors of the second region is lower than that of the first region,
wherein a part of the insulating layer overlaps with the second region,
wherein the first surface of the insulating layer in the part of the insulating layer is in contact with the gate electrode,
wherein the second surface of the insulating layer in the part of the insulating layer is substantially aligned with an interface between the first region and the second region, and
wherein the gate insulating film is over and in contact with the first region and the second region.

8. The semiconductor device according to claim 7 ,
wherein the channel formation region includes oxygen-defect-inducing factors.

9. The semiconductor device according to claim 8 ,
wherein a concentration of the oxygen-defect-inducing factors in the channel formation region is less than 1×10 14 atoms/cm 3 .

10. The semiconductor device according to claim 7 ,
wherein the gate electrode overlaps with the channel formation region,
wherein the insulating layer covers the oxide semiconductor layer, the gate insulating layer, and the gate electrode layer, and
wherein the source electrode layer is electrically connected to the source region and the drain electrode layer is electrically connected to the drain region.

11. The semiconductor device according to claim 7 , wherein the oxygen-defect-inducing factors are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

12. The semiconductor device according to claim 7 ,
wherein the channel formation region has n-type conductivity.

13. A semiconductor device comprising:
an oxide semiconductor layer including a channel formation region and source and drain regions;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer;
an insulating layer over the gate electrode layer; and
a source electrode layer and a drain electrode layer over the insulating layer,
wherein each of the source and drain regions includes oxygen defects due to elements,
wherein the gate insulating film is over and in contact with the source and drain regions,
wherein a concentration of the elements of the source region or the drain region is higher than that of the channel formation region, and
wherein the elements are one or more selected from the group consisting of titanium, tungsten, and molybdenum.

14. The semiconductor device according to claim 13 ,
wherein the channel formation region includes the elements.

15. The semiconductor device according to claim 13 ,
wherein the gate electrode overlaps with the channel formation region,
wherein the insulating layer covers the oxide semiconductor layer, the gate insulating layer, and the gate electrode layer, and
wherein the source electrode layer is electrically connected to the source region and the drain electrode layer is electrically connected to the drain region.

Assignees

• Yamazaki Shunpei
• Koezuka Junichi
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koezuka Junichi

Classifications

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P30/22

  using masks · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/22

  using physical deposition, e.g. vacuum deposition or sputtering · CPC title