Substrate backside texturing

US9711419B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9711419-B2
Application numberUS-201514833044-A
CountryUS
Kind codeB2
Filing dateAug 22, 2015
Priority dateAug 6, 2014
Publication dateJul 18, 2017
Grant dateJul 18, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for adjusting backside texturing of a semiconductor substrate that is processed on a photolithography tool, comprising: determining one or more contact areas on the photolithography tool at which the backside of the semiconductor substrate contacts the photolithography tool; determining a backside surface texturing for the semiconductor substrate that is based, at least in part, on: a frequency of backside features of the semiconductor substrate at one or more portions of the semiconductor substrate, an amplitude of the backside features at the one or more portions of the semiconductor substrate, or a size of the one or more contact areas; determining a target backside surface texturing that reduces the coefficient of friction between the backside of the substrate and the one or more contact areas of the photolithographic tool at which the backside of the substrate contacts the photolithographic tool based on sizes of the one or more contact areas; and processing the backside of the semiconductor substrate to obtain the target backside surface texturing. 2. The method of claim 1 , wherein the processed backside contacts each of the one or more contact area at a frequency of no more than 70 contacts per millimeter. 3. The method of claim 2 , wherein the amplitude of the backside features varies by no more than 10 nm with respect to each other. 4. The method of claim 1 , wherein the processing comprises ablating the backside features with a laser beam. 5. The method of claim 4 , wherein the laser beam comprises a wavelength between 300 nm and 1400 nm. 6. The method of claim 5 , wherein the laser beam comprises a dose of about 150 J/cm 2 . 7. The method of claim 6 , wherein the processing comprises a laser beam overlap of no more than 10 μm. 8. The method of claim 6 , wherein the processing comprises removing one or more films and/or a material of the backside with at least one chemical agent in conjunction with the polishing or laser treatment. 9. The method of claim 1 , wherein determining the target backside surface texturing is further based on the determined backside surface texturing. 10. A method of reducing lithographic distortion comprising: determining a target backside surface texturing that reduces a coefficient of friction between a backside of a semiconductor substrate and one or more contact areas of a lithographic tool at which the backside of the semiconductor substrate contacts the photolithographic tool based on sizes of the one or more contact areas; texturizing a backside of the semiconductor substrate according to the determined target backside surface texturing; and performing a lithographic process on the semiconductor substrate having the texturized backside with the lithographic tool which supports the substrate at the one or more contact areas. 11. The method of claim 10 , wherein the texturizing comprises applying a pulsed laser to one or more films from a backside of the semiconductor substrate. 12. The method of claim 11 , wherein the pulsed laser comprises a wavelength between 300 nm and 1400 nm. 13. The method of claim 10 , wherein the texturized backside contacts each of the one or more contact areas at a frequency of 5-10 contacts per micron. 14. The method of claim 10 , wherein the texturized backside has features that vary in distance in a direction perpendicular to a surface of the semiconductor substrate by no more than 10 nm. 15. The method of claim 10 , further comprising: producing an image on a front surface of the substrate; measuring variations in the image from a reference; and producing a modified image on a front surface of a subsequent substrate that varies from the image in accordance with the variations. 16. The method of claim 10 , wherein determining the target backside surface texturing is further based on a preexisting backside surface texturing.

Assignees

Inventors

Classifications

  • Photolithographic processes · CPC title

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

  • of semiconductor materials · CPC title

  • H10P74/203Primary

    Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9711419B2 cover?
Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.
Who is the assignee on this patent?
Tokyo Electron Ltd
What technology area does this patent fall under?
Primary CPC classification H10P76/2041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).