Power trench MOSFET with improved unclamped inductive switching (UIS) performance and preparation method thereof

Patent metadata

Field	Value
Publication number	US-9704948-B2
Application number	US-201414455877-A
Country	US
Kind code	B2
Filing date	Aug 9, 2014
Priority date	Aug 9, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole.

First claim

What is claimed is:

1. A trench type power semiconductor device comprising:
a semiconductor substrate comprising a bottom substrate and an epitaxial layer atop the bottom substrate;
an isolation trench formed a termination area in the epitaxial layer and active trenches formed in an active area in the epitaxial layer, wherein an intermediate area locates between an outermost active trench close to the isolation trench and the isolation trench;
an insulation layer lined at bottoms and on side walls of the isolation trench and the active trenches, and conductive material deposited in the isolation trench and in the active trenches;
an insulation passivation layer covering the semiconductor substrate;
a first contact hole passing through the insulation passivation layer and extending downward into a mesa of the active area, and a second contact hole passing through the insulation passivation layer and extending downward into a mesa of the intermediate area; wherein
the first contact hole is deeper and wider than the second contact hole.

2. The trench type power semiconductor device of claim 1 further comprises first, second and third metal plugs, wherein the first and second metal plugs respective formed in the first contact hole and the second contact hole, the third metal plug formed in a third hole through the insulation passivation layer and in alignment with the conductive material deposited in the isolation trench, wherein the first, second and third metal plugs are in electrical contact with a top metal electrodes in the active area and the intermediate area.

3. The trench type power semiconductor device of claim 1 , wherein the semiconductor substrate has a first conductive type, a body layer of a second conductive type opposite to the first conductivity type is formed atop the epitaxial layer, a source layer of the first conductivity type is formed at a top portion of the body layer in the active area, wherein the first contact hole and the second contact hole end in the body layer.

4. The trench type power semiconductor device of claim 3 further comprising body contact implants of the second conductivity type formed around bottoms of the first contact hole and the second contact hole wherein a depth and a diffusion range of the body contact implant around the bottom of the second contact hole are smaller than a depth and a diffusion range of the body contact implant around the bottom of the first contact hole respectively.

5. The trench type power semiconductor device of claim 1 , wherein the conductive material in each of the active trenches comprise a shielding gate located at a lower part of the active trench and a control gate located at an upper part of the active trench, and an insulation layer is arranged between the shielding gate and the contact gate, and wherein the shielding gate and the conductive material in the isolation trench have the same potential.

6. A trench type power semiconductor device comprising:
a semiconductor substrate comprising a bottom substrate and an epitaxial layer atop the bottom substrate;
a first mesa formed between a first trench and a second trench extending from a top surface of the epitaxial layer into the epitaxial layer;
a second mesa formed between a third trench and the second trench from the top surface of the epitaxial layer into the epitaxial layer;
a source region having a conductivity type same as the epitaxial layer formed from the top surface of the epitaxial layer to a first depth in the first mesa, the source region extending through an entire width of the first mesa;
a first body region having a conductivity type opposite the epitaxial layer formed in the first mesa from a bottom of the source region to a second depth deeper than the first depth, the first body region extending through the entire width of the first mesa;
a second body region formed in the second mesa from the top surface of the epitaxial layer to a third depth, the second body region extending through an entire width of the second mesa;
a first contact hole filled with a conductive material formed from the top surface of the epitaxial layer through the source region reaching the first body region;
a second contact hole filled with a conductive material formed from the top surface of the epitaxial layer into the second body region, wherein the second contact hole being narrower and shallower than the first contact hole.

7. The trench type power semiconductor device of claim 6 , wherein the first and second trenches being filled with a conductive material insulated from the epitaxial layer functioning as trenched gate.

8. The trench type power semiconductor device of claim 7 , wherein the third trench being filled with a conductive material insulated from the epitaxial layer functioning as a gate runner.

9. The trench type power semiconductor device of claim 6 , wherein the third depth of the second body region being substantially the same as the second depth of the first body region.

10. The trench type power semiconductor device of claim 9 further comprising a body type doped region more heavily doped than the first body region at a bottom of the first contact hole.

11. The trench type power semiconductor device of claim 10 further comprising a body type doped region more heavily doped than the second body region at a bottom of the second contact hole.

12. The trench type power semiconductor device of claim 6 wherein the first trench and the second trench being enclosed by the third trench.

13. The trench type power semiconductor device of claim 6 the conductive material filling the first contact hole being electrically connected to the conductive material filling the second contact hole.

14. The trench type power semiconductor device of claim 6 , wherein the third trench being filled with a conductive material insulated from the epitaxial layer.

15. The trench type power semiconductor device of claim 14 further comprising a third contact hole open through a dielectric material on top of the conductive material inside the third trench, wherein the third contact hole being filled with a conductive material connected to the conductive material filling the third trench.

Assignees

• Alpha & Omega Semiconductor
• Alpha & Omega Semiconductor (Cayman) Ltd

Inventors

• Ding Yongping
• Yilmaz Hamza
• Wang Xiaobin
• Bobde Madhur

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H01L29/0626 Primary

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic