SiC transient voltage suppressor

Patent metadata

Field	Value
Publication number	US-9478606-B2
Application number	US-201514622309-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 13, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments.

First claim

The invention claimed is:

1. A transient voltage suppressor, comprising:
a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;
a backside conductive contact on a backside of the substrate;
an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;
a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;
a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and
a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;
the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;
in which:
the epitaxial SiC layer has an upper surface;
the central active area includes an array of spaced-apart trenches each having a bottom spaced below the upper surface with first implants of the second dopant type in the bottom of each trench; and
the peripheral termination area includes an array of second implants of the second dopant type subjacent the upper surface of the epitaxial SiC layer;
the first implants extending to a depth in the epitaxial SiC layer greater than a depth of the second implants so as to thereby provide the lower breakdown voltage in the central active area than a breakdown voltage in the peripheral termination area.

2. A transient voltage suppressor according to claim 1 capable of a clamping voltage greater than 500V.

3. A transient voltage suppressor according to claim 1 capable of a clamping voltage greater than 100V.

4. A transient voltage suppressor according to claim 1 in which the frontside conductive contact includes a Schottky metal layer.

5. A transient voltage suppressor, comprising:
a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;
a backside conductive contact on a backside of the substrate;
an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;
a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;
a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and
a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;
the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;
in which:
the epitaxial SiC layer includes a first epitaxial sublayer of the second doping concentration and a second epitaxial sublayer of a third doping concentration greater than the second doping concentration atop the first epitaxial sublayer, each epitaxial sublayer having an upper surface;
the central active area being formed subjacent the upper surface of the second epitaxial sublayer and the peripheral termination area being formed subjacent the upper surface of the first epitaxial sublayer.

6. A transient voltage suppressor according to claim 5 in which the frontside conductive contact includes a Schottky metal layer.

7. A transient voltage suppressor, comprising:
a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;
a backside conductive contact on a backside of the substrate;
an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;
a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;
a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and
a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;
the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;
in which:
the epitaxial SiC layer includes a first epitaxial sublayer of the second doping concentration and a second epitaxial sublayer of a third doping concentration between the first epitaxial sublayer and the substrate, the third doping concentration less than the first doping concentration of the substrate and greater than the second doping concentration.

8. A transient voltage suppressor according to claim 7 in which the frontside conductive contact includes a Schottky metal layer.

9. A transient voltage suppressor, comprising:
a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;
a backside conductive contact on a backside of the substrate;
an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;
a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;
a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and
a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;
the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;
in which the second doping concentration in the epitaxial SiC layer has a graded dopant profile spanning an interface between the substrate and the epitaxial SiC layer.

10. A transient voltage suppressor according to claim 9 in which the frontside conductive contact includes a Schottky metal layer.

11. A transient voltage suppressor, comprising:
a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;
a backside conductive contact on a backside of the substrate;
an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;
a central active area including a region of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;
a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the region of the second dopant type; and
a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the cent

Assignees

• Microsemi Corp

Inventors

• Sdrulla Dumitru
• Odekirk Bruce
• Walters Cecil Kent

Classifications

• H10D62/8303

  Diamond · CPC title

• H10D8/825

  Diodes having bulk potential barriers, e.g. Camel diodes, planar doped barrier diodes or graded bandgap diodes · CPC title

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D64/111

  Field plates · CPC title