Magnetoresistive random access memory cell and fabricating the same

Patent metadata

Field	Value
Publication number	US-9685604-B2
Application number	US-201514841311-A
Country	US
Kind code	B2
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A magnetoresistive random-access memory (MRAM) cell includes a free layer having a variable magnetic polarity, wherein the free layer has a first width; a pin layer having a fixed magnetic polarity, wherein the pin layer has the first width; a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width; a top electrode layer located above the free layer, the pin layer, and the barrier layer; a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and a capping layer encapsulating a sidewall of the barrier layer.

First claim

What is claimed is:

1. A method comprising:
forming a stack of film disposed over a bottom electrode layer, wherein the stack of film includes a pin layer disposed over the bottom electrode layer, a barrier layer disposed over the pin layer, a free layer disposed over the barrier layer, and a top electrode layer disposed over the free layer;
forming a patterned hard mask over the top electrode layer;
etching the top electrode layer and the free layer by using the patterned hard mask as a first etch mask;
forming a first capping layer along sidewalls of the top electrode layer and the free layer;
etching the barrier layer thereby forming a recessed barrier layer that is located between the first capping layer and the pin layer;
forming a second capping layer over the first capping layer and extending along sidewalls of the recessed barrier layer; and
etching the pin layer and the bottom electrode layer by using the second capping layer as a second etch mask.

2. The method of claim 1 , further comprising forming an inter-metal dielectric layer over the patterned hard mask and along sidewalls of the second capping layer, the pin layer, and the bottom electrode layer.

3. The method of claim 1 , wherein the barrier layer serves as an etch-stop layer during etching of the top electrode layer and the free layer.

4. The method of claim 1 , wherein forming the first capping layer along sidewalls of the top electrode layer and the free layer includes:
depositing the first capping layer over the patterned hard mask, along sidewalls of the top electrode layer and the free layer, and over a top surface of the barrier layer; and
removing the first capping layer over the patterned hard mask to expose a portion of the patterned hard mask.

5. The method of claim 1 , wherein etching the barrier layer thereby forming the recessed barrier layer includes using a plasma-assisted etching process.

6. The method of claim 5 , wherein etching the barrier layer thereby forming the recessed barrier layer includes using methanol during the etching.

7. The method of claim 5 , wherein etching the barrier layer thereby forming the recessed barrier layer includes etching the barrier layer without a direct-current (DC) bias.

8. The method of claim 1 , wherein etching the barrier layer thereby forming a recessed barrier layer includes forming recesses on either side of the recessed barrier layer, and
wherein forming the second capping layer over the first capping layer and extending along sidewalls of the recessed barrier layer includes forming the second capping layer in the recesses on either side of the recessed barrier layer.

9. A method comprising:
forming a stack of film disposed over a bottom electrode layer, wherein the stack of film includes a free layer disposed over the bottom electrode layer, a barrier layer disposed over the free layer, a pin layer disposed over the barrier layer, and a top electrode layer disposed over the pin layer;
forming a patterned hard mask over the top electrode layer;
etching the top electrode layer and the pin layer by using the patterned hard mask as a first etch mask;
etching the barrier layer thereby forming a recess located between the free layer and the pin layer;
forming a first capping layer along sidewalls of the top electrode layer, the pin layer, and the etched barrier layer;
etching the free layer by using the first capping layer as a second etch mask;
forming a second capping layer over the first capping layer and extending along a sidewall of the etched free layer; and
etching the bottom electrode layer by using the second capping layer as a third etch mask.

10. The method of claim 9 , further comprising forming an inter-metal dielectric layer over the patterned hard mask and along sidewalls of the second capping layer and the bottom electrode layer.

11. The method of claim 9 , wherein the free layer serves as an etch-stop layer during the etching the top electrode layer, the pin layer, and the barrier layer.

12. The method of claim 9 , wherein forming the first capping layer along sidewalls of the top electrode layer, the pin layer, and the etched barrier layer includes:
depositing the first capping layer over the patterned hard mask, along sidewalls of the top electrode layer, the pin layer, and the etched barrier layer, and over a top surface of the free layer; and
removing the first capping layer over the patterned hard mask to expose a portion of the patterned hard mask.

13. The method of claim 9 , wherein the etching the barrier layer includes using a plasma-assisted etching process.

14. The method of claim 13 , wherein etching the barrier layer includes using methanol during the etching.

15. The method of claim 13 , wherein etching the barrier layer includes etching the barrier layer without a direct-current (DC) bias.

16. The method of claim 9 , wherein forming the first capping layer along sidewalls of the top electrode layer, the pin layer, and the etched barrier layer sidewalls includes forming the first capping layer in the recess located between the free layer and the pin layer.

17. The method of claim 9 , wherein the first capping layer and the second capping layer are formed of different materials.

18. A magnetoresistive random-access memory (MRAM) cell comprising:
a free layer having a variable magnetic polarity, wherein the free layer has a first width;
a pin layer having a fixed magnetic polarity, wherein the pin layer has a third width that is different than the first width;
a barrier layer located between the pin layer and the free layer, wherein the barrier layer has a second width that is less than the first width;
a top electrode layer located above the free layer, the pin layer, and the barrier layer;
a bottom electrode layer located beneath the free layer, the pin layer, and the barrier layer; and
a capping layer encapsulating a sidewall of the barrier layer.

19. The MRAM cell of claim 18 , wherein the barrier layer is disposed over the free layer and below the pin layer, and
wherein the capping layer is disposed along sidewalls of the top electrode layer, the pin layer, the barrier layer, and the free layer.

20. The MRAM cell of claim 18 , wherein the barrier layer is disposed over the pin layer and below the free layer, and
wherein the capping layer is disposed along sidewalls of the top electrode layer, the free layer, the barrier layer, and a top surface of the pin layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Wei-Hang
• Liu Shih-Chang

Classifications

• H01L43/10

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/08

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic