MRAM element having improved data retention and low writing temperature

Patent metadata

Field	Value
Publication number	US-9331268-B2
Application number	US-201314405918-A
Country	US
Kind code	B2
Filing date	Jun 7, 2013
Priority date	Jun 8, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A thermally assisted switching MRAM element including a magnetic tunnel junction including a reference layer having a reference magnetization; a storage layer having a storage magnetization; a tunnel barrier layer included between the storage layer and the reference layer; and a storage antiferromagnetic layer exchange-coupling the storage layer such as to pin the storage magnetization at a low temperature threshold and to free it at a high temperature threshold. The antiferromagnetic layer includes: at least one first antiferromagnetic layer having a first storage blocking temperature, and at least one second antiferromagnetic layer having a second storage blocking temperature; wherein the first storage blocking temperature is below 200° C. and the second storage blocking temperature is above 250° C. The MRAM element combines better data retention compared with known MRAM elements with low writing mode operating temperature.

First claim

The invention claimed is:

1. A thermally assisted switching MRAM element comprising a magnetic tunnel junction including a reference layer having a reference magnetization; a storage layer having a storage magnetization; a tunnel barrier layer included between the storage layer and the reference layer; and a storage antiferromagnetic layer exchange-coupling the storage layer such as to pin the storage magnetization at a low temperature threshold and to free it at a high temperature threshold;
the storage antiferromagnetic layer comprising at least one first antiferromagnetic layer having a first storage blocking temperature, and at least one second antiferromagnetic layer having a second storage blocking temperature;
the first storage blocking temperature being below 200° C. and the second storage blocking temperature being above 250° C.

2. MRAM element according to claim 1 , wherein said at least one first antiferromagnetic layer comprises a FeMn-based alloy.

3. MRAM element according to claim 1 , wherein said at least one second antiferromagnetic layer comprises a IrMn, PtMn or NiMn-based alloy.

4. MRAM element according to claim 1 , wherein the storage antiferromagnetic layer comprises a plurality of the first antiferromagnetic layer and a plurality of the second antiferromagnetic layer, wherein each of said plurality of the first antiferromagnetic layer alternates with each of said plurality of the second antiferromagnetic layers.

5. MRAM element according to claim 4 , wherein the first antiferromagnetic layer has a thickness comprised between 0.1 nm and 5 nm and the second antiferromagnetic layer has a thickness comprised between 0.1 nm and 5 nm.

6. MRAM element according to claim 4 , wherein the first antiferromagnetic layer has a thickness comprised between 0.5 nm and 5 nm and the second antiferromagnetic layer has a thickness comprised between 0.5 nm and 5 nm.

7. MRAM element according to claim 1 , wherein the storage antiferromagnetic layer has a thickness comprised between 5 nm and 50 nm, but preferably between 5 nm and 10 nm.

8. MRAM element according to claim 1 , wherein said at least one first antiferromagnetic layer is in contact with the storage layer.

9. MRAM element according to claim 1 , wherein the magnetic tunnel junction further comprises an antiferromagnetic reference layer exchange-coupling the reference layer such as to pin the reference magnetization below a reference blocking temperature of the antiferromagnetic reference layer.

10. MRAM device; comprising a plurality of MRAM elements, each MRAM element comprising a magnetic tunnel junction including a reference layer having a reference magnetization; a storage layer having a storage magnetization; a tunnel barrier layer included between the storage layer and the reference layer; and a storage antiferromagnetic layer exchange-coupling the storage layer such as to pin the storage magnetization at a low temperature threshold and to free it at a high temperature threshold;
the storage antiferromagnetic layer comprising at least one first antiferromagnetic layer having a first storage blocking temperature, and at least one second antiferromagnetic layer having a second storage blocking temperature;
the first storage blocking temperature being below 200° C. and the second storage blocking temperature being above 250° C.

Assignees

• Crocus Technology Sa

Inventors

• Prejbeanu Ioan Lucian
• Dieny Bernard
• Ducruet Clarisse
• Lombard Lucien

Classifications

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/16 Primary

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• H01L43/02

  Electricity · mapped topic

• H01L43/08 Primary

  Electricity · mapped topic