Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US9305628B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9305628-B2 |
| Application number | US-201314649591-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 2, 2013 |
| Priority date | Dec 7, 2012 |
| Publication date | Apr 5, 2016 |
| Grant date | Apr 5, 2016 |
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MRAM cell including a magnetic tunnel junction including a sense layer, a storage layer, a tunnel barrier layer and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature. The sense layer is arranged such that the sense magnetization can be switched from a first stable direction to another stable direction opposed to the first direction. The switched sense magnetization generates a sense stray field being large enough for switching the storage magnetization according to the switched sense magnetization, when the magnetic tunnel junction is heated at the writing temperature. The disclosure also relates to a method for writing to the MRAM cell with increased reliability and reduced power consumption.
Opening claim text (preview).
The invention claimed is: 1. Method for writing to the MRAM cell comprising a magnetic tunnel junction including a sense layer having a sense magnetization; a storage layer having a storage magnetization; a tunnel barrier layer comprised between the sense and the storage layers; and an antiferromagnetic layer exchange-coupling the storage layer such that the storage magnetization can be pinned when the antiferromagnetic layer is below a critical temperature and freely varied when the antiferromagnetic layer is heated at or above the critical temperature; said sense layer is arranged such that the sense magnetization can be switched from a first stable direction to another stable direction opposed to the first direction; the switched sense magnetization generating a sense stray field being large enough for switching the storage magnetization according to the switched sense magnetization, when the magnetic tunnel junction is heated at the writing temperature; the method comprising: switching the sense magnetization from a first direction to a second direction opposed to the first direction, the switched sense magnetization generating a local sense stray field; passing a heating current pulse in the magnetic tunnel junction for heating the magnetic tunnel junction at or above the critical temperature such as to switch the storage magnetization in accordance with the sense stray field; and turning off the write magnetic field; the heating current pulse being passed after turning off the write magnetic field. 2. The method according to claim 1 , wherein said switching the sense magnetization comprises applying a write magnetic field adapted for switching the sense magnetization according to the direction of the write magnetic field. 3. The method according to claim 1 , further comprising turning off the heating current pulse such as to cool the magnetic tunnel junction below the critical temperature and pin the storage magnetization in the written state. 4. The method according to claim 1 , wherein the MRAM cell further comprises a current line in electrical communication with one end of the magnetic tunnel junction; and wherein the heating current pulse is passed in the magnetic tunnel junction via the current line. 5. The method according to claim 4 , wherein said applying a write magnetic field comprises passing a write current in the current line. 6. The method according to claim 1 , wherein the sense magnetization is larger than the net storage magnetization. 7. The method according to claim 1 , wherein the sense layer has a coercive field being higher than a storage magnetic stray field induced by the storage magnetization. 8. The method according to claim 1 , wherein said storage magnetization comprises a first storage layer, a spacer layer and a second storage layer; the storage magnetization comprising a first storage magnetization of the first storage layer and a second storage magnetization of the second storage layer, the spacer layer magnetically coupling the first storage magnetization antiparallel with the second storage magnetization; the sense stray field inducing a magnetic coupling between the sense magnetization and the first and second storage magnetizations in a closed magnetic flux configuration.
Timing circuits or methods · CPC title
details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title
Writing or programming circuits or methods · CPC title
the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title
Reading or sensing circuits or methods · CPC title
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