MRAM integration techniques for technology scaling

Patent metadata

Field	Value
Publication number	US-9406875-B2
Application number	US-201314109200-A
Country	US
Kind code	B2
Filing date	Dec 17, 2013
Priority date	Dec 17, 2013
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

First claim

What is claimed is:

1. A magnetoresistive random-access memory (MRAM) comprising:
a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements,
wherein, the MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer, wherein the MTJ is in direct physical contact with the top via,
wherein the MTJ extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer, and one or more top cap layers configured to separate the common IMD layer and the top IMD layer.

2. The MRAM of claim 1 , wherein the MTJ comprises a free layer, a barrier layer, and a pinned layer.

3. The MRAM of claim 1 , wherein the MTJ comprises a hard mask connected to a top electrode, such that the MTJ is connected to the top via through the top electrode.

4. The MRAM of claim 3 comprising two bottom cap layers configured to separate the common IMD layer and the bottom IMD layer, and wherein a bottom electrode of the MTJ is connected to the bottom metal line through a bottom electrode contact, wherein the bottom electrode contact extends through both of the two bottom cap layers.

5. The MRAM of claim 4 , fabricated with three masks, wherein a first mask is used for formation of the bottom electrode contact, a second mask is used for formation the MTJ, and a third mask is used for formation the top electrode.

6. The MRAM of claim 3 comprising two bottom cap layers configured to separate the common IMD layer and the bottom IMD layer, and wherein a bottom electrode of the MTJ is connected to the bottom metal line through a bottom electrode contact, wherein the bottom electrode contact extends through only one of the two bottom cap layers.

7. The MRAM of claim 1 , wherein the MTJ comprises a hard mask such that the MTJ is connected to the top via directly through the hard mask.

8. The MRAM of claim 7 , comprising two bottom cap layers configured to separate the common IMD layer and the bottom IMD layer, and wherein a bottom electrode of the MTJ is connected to the bottom metal line through a bottom electrode contact, wherein the bottom electrode contact extends through both of the two bottom cap layers.

9. The MRAM of claim 8 , fabricated with two masks, wherein a first mask is used for formation of the bottom electrode contact, and a second mask is used for formation of the MTJ.

10. The MRAM of claim 7 , comprising two bottom cap layers configured to separate the common IMD layer and the bottom IMD layer, and wherein a bottom electrode of the MTJ is connected to the bottom metal line through a bottom electrode contact, wherein the bottom electrode contact extends through only one of the two bottom cap layers.

11. The MRAM of claim 1 , wherein the one or more logic elements comprise one or more of a via and a metal line formed in the common IMD layer.

12. The MRAM of claim 1 , further comprising a protective side cap configured to surround the MTJ.

13. A magnetoresistive random-access memory (MRAM) device comprising:
a magnetic storage means formed in a common insulating means with one or more means for performing a logic function,
wherein, the magnetic storage means is connected to a bottom metallic means in a bottom insulating means and a top through interconnection means connected to a top insulating means, wherein the magnetic storage means is in direct physical contact with the top through interconnection means, and
wherein a magnetic tunnel junction (MTJ) extends between bottom means for separating the common insulating means and the bottom insulating means and one or more top means for separating the common insulating means and the top insulating means.

Assignees

• Qualcomm Inc

Inventors

• Li Xia
• Lu Yu
• Kang Seung Hyuk

Classifications

• H01L43/08

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• G11C11/1659

  Cell access · CPC title