High density low power GSHE-STT MRAM

Patent metadata

Field	Value
Publication number	US-9230627-B2
Application number	US-201414451510-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Jan 28, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C).

First claim

What is claimed is:

1. A memory element comprising:
a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, the GSHE-STT MRAM element comprising:
a GSHE strip formed between a first terminal (A) and a second terminal (B); and
a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip and a fixed layer of the MTJ coupled to a third terminal (C);
wherein an orientation of an easy axis of the free layer is substantially perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal,
such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the fixed layer.

2. The memory element of claim 1 , wherein the MTJ is switched into a high resistance state representing logic 1, when the second charge current is injected through the third terminal into the MTJ; and the MTJ is switched into a low resistance representing logic 0, when the second charge current is injected through the third terminal into the MTJ.

3. The memory element of claim 2 , wherein in the high resistance state, the free layer is switched to be anti-aligned or anti-parallel to a fixed layer of the MTJ and in the low resistance state, the free layer is switched to be aligned or parallel to the fixed layer.

4. The memory element of claim 1 , further comprising an access transistor, wherein a drain/source terminal of the access transistor is connected to the third terminal.

5. The memory element of claim 1 wherein the MTJ is an in-plane MTJ and the orientation of the easy axis of the free layer is in the same plane as the magnetization created by electrons traversing the GSHE strip.

6. The memory element of claim 1 wherein the MTJ is a perpendicular MTJ and the orientation of the easy axis of the free layer is substantially perpendicular to the GSHE strip.

7. A method of forming a memory element, the method comprising:
forming a giant spin Hall effect (GSHE) strip between a first terminal (A) and a second terminal (B) of the memory element;
forming a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip;
coupling a fixed layer of the MTJ to a third terminal (C) of the memory element; and
aligning the MTJ such that orientation of an easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal,
such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the fixed layer.

8. The method of claim 7 , comprising switching the MTJ into a high resistance state representing logic 1, when the second charge current is injected through the third terminal into the MTJ; and switching the MTJ into a low resistance representing logic 0, when the second charge current is injected through the third terminal into the MTJ.

9. The method of claim 8 , comprising in the high resistance state, switching the free layer to be anti-aligned or anti-parallel to the fixed layer of the MTJ and in the low resistance state, switching the free layer to be aligned or parallel to the fixed layer.

10. The method of claim 7 , further comprising connecting a drain/source terminal of an access transistor to the third terminal.

11. The method of claim 7 , comprising forming the MTJ as an in-plane MTJ, wherein the orientation of the easy axis of the free layer is in the same plane as the magnetization created by electrons traversing the GSHE strip.

12. The method of claim 7 , comprising forming the MTJ as a perpendicular MTJ, wherein the orientation of the easy axis of the free layer is substantially perpendicular to the GSHE strip.

13. A memory comprising:
a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) means, the GSHE-STT MRAM means comprising:
a GSHE means for coupling a first terminal (A) and a second terminal (B); and
a magnetic tunnel junction (MTJ) coupled to the GSHE means such that a free layer of the MTJ interfaces the GSHE means; and
means for coupling a fixed layer of the MTJ to a third terminal (C);
wherein an orientation of an easy axis of the free layer is substantially perpendicular to the magnetization created by electrons traversing the GSHE means between the first terminal and the second terminal,
such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ.

14. The memory of claim 13 , comprising means for switching the MTJ into a high resistance state representing logic 1, when the second charge current is injected through the third terminal into the MTJ; and means for switching the MTJ into a low resistance representing logic 0, when the second charge current is extracted from the third terminal out of the MTJ.

15. The memory of claim 14 , comprising in the high resistance state, means for switching the free layer to be anti-aligned or anti-parallel to the fixed layer of the MTJ and in the low resistance state, means for switching the free layer to be aligned or parallel to the fixed layer.

16. The memory of claim 13 , further comprising means for coupling a drain/source terminal of an access transistor to the third terminal.

Assignees

• Qualcomm Inc

Inventors

• Wu Wenqing
• Madala Raghu Sagar
• Yuen Kendrick Hoy Leong
• Arabi Karim

Classifications

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659

  Cell access · CPC title

• H01L43/14

  Electricity · mapped topic