Multilayer printed circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9668362-B2
Application number	US-201414466611-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Aug 28, 2013
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

When laminating two resin films so that sides where the conductive patterns are not formed face each other, and when laminating other resin films so that sides where the conductive patterns are formed and the sides where the conductive patterns are not formed to face each other, a plurality of resin films each of which has the same resin thickness are used for the other resin films, and two resin films having a sum of resin thickness that is the same as the resin thickness of the other single resin film are used for the two resin films. Accordingly, dielectric thicknesses between the conductive patterns formed in the adjoining resin films can be made even so that an impedance can be calculated easily, and it becomes possible to ease the circuit design.

First claim

What is claimed is:

1. A multilayer printed circuit board comprising: a plurality of resin films laminated in a lamination direction, each resin film having a via, the plurality of resin films having a top surface and a bottom surface; and conductive patterns formed only on one side of each resin film, the conductive patterns including a first conductive pattern at the top surface, a second conductive pattern at the bottom surface, and a third conductive pattern at a center of the plurality of resin film in the lamination direction, the third conductive pattern constituting a transmission line of a high-frequency signal of 3 kHz or higher, the first conductive pattern and the second conductive pattern being connected through the vias in the resin films and constituting ground lines of the high-frequency signal, wherein, among the plurality of the resin films, two resin films are laminated so that sides where the conductive patterns are not formed face each other; other resin films among the plurality of the resin films except for these two resin films have a same resin thickness and are laminated so that sides where the conductive patterns are formed and the sides where the conductive patterns are not formed face each other; all intervals between the conductive patterns in a laminating direction in a portion where the other resin films are laminated are the same; and intervals between the conductive patterns in the laminating direction in a portion where the two resin films are laminated are the same as the intervals in the portion where the other resin films are laminated by configuring the two resin films to have a sum of their thickness to be the same as the resin thickness of any single one of the other resin films.

Assignees

• Denso Corp

Inventors

• Harada Toshikazu
• Ishikawa Yoshichika

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H05K1/025

  Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance (H05K1/024 and H05K1/0243 take precedence; for semiconductor devices H10W44/20) · CPC title

• H05K3/4697

  having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title

• H05K1/186

  manufactured by mounting on or connecting to patterned circuits before or during embedding · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title