Ground termination with dampened resonance
US-9210812-B2 · Dec 8, 2015 · US
Method for manufacturing layered electronic devices
US2016007462A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016007462-A1 |
| Application number | US-201414333856-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 17, 2014 |
| Priority date | Jul 7, 2014 |
| Publication date | Jan 7, 2016 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
A method for fabricating printed electronics includes printing a trace of an electrical component on a first substrate to form a first layer. The method further includes printing a trace of an electrical component on at least one additional substrate to form at least one additional layer. The first layer is stacked with the at least one additional layer to create an assembled electrical device. At least one of the layers is modified after printing.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method for fabricating printed electronics: printing a trace of an electrical component on a first substrate to form a first layer; printing a trace of an electrical component on at least one additional substrate to form at least one additional layer; and stacking the first layer with the at least one additional layer to create an assembled electrical device, wherein at least one of the layers is modified after printing. 2 . The method of claim 1 , wherein the trace of the electrical component is at least one of electrically conductive, semiconductive, or insulating material. 3 . The method of claim 2 , wherein the printed material is at least one of an ink, paste, slurry, dispersion, solution or a powder. 4 . The method of claim 1 , wherein printing includes printing the first layer of the electrical device including multiple electrical components with varying electrical functionalities. 5 . The method of claim 1 , wherein modifying includes shrinking the substrates for the first layer and the at least one additional layer to a target size prior to stacking by heating the substrates at a predetermined temperature for a predetermined duration based on properties of the substrates. 6 . The method of claim 1 , further including shrinking the assembled electrical device to a target size by heating the assembled electrical device at a predetermined temperature for a predetermined duration based on properties of the substrates. 7 . The method of claim 1 , further including shrinking the substrates for the first layer and the at least one additional layer to a target size prior to stacking by heating the substrates at a predetermined temperature for a predetermined duration based on properties of the substrates and shrinking the assembled electrical device to a target size by heating the assembled electrical device at a predetermined temperature for a predetermined duration based on properties of the substrates. 8 . The method of claim 1 , wherein modifying includes curing, cutting, embossing, stamping, plating and/or etching the substrate. 9 . The method of claim 1 , wherein stacking includes rolling the first layer and the at least one additional layer. 10 . The method of claim 1 , wherein stacking includes vertical layering of the first layer and the at least one additional layer. 11 . The method of claim 1 , wherein stacking includes positioning vertical interconnectors between at least two different layers. 12 . An electrical device manufactured by the process comprising: printing a trace of an electrical component on a first substrate to form a first layer; printing a trace of an electrical component on at least one additional substrate to form at least one additional layer; and stacking the first layer with the at least one additional layer to create an assembled electrical device, wherein at least one of the layers is modified after printing. 13 . The electrical device of claim 12 , wherein printing includes printing the first layer of the electrical device including multiple electrical components with varying electrical functionalities.
Assignees
Inventors
Classifications
Cured, e.g. vulcanised, cross-linked · CPC title
Lamination · CPC title
Multilayer circuits · CPC title
characterised by the heating method · CPC title
Process of electroless plating · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2016007462A1 cover?
- A method for fabricating printed electronics includes printing a trace of an electrical component on a first substrate to form a first layer. The method further includes printing a trace of an electrical component on at least one additional substrate to form at least one additional layer. The first layer is stacked with the at least one additional layer to create an assembled electrical device.…
- Who is the assignee on this patent?
- Hamilton Sundstrand Corp
- What technology area does this patent fall under?
- Primary CPC classification H05K1/16. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jan 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).