Method of forming self-aligned metal lines and vias

US9607893B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9607893-B1
Application numberUS-201615202949-A
CountryUS
Kind codeB1
Filing dateJul 6, 2016
Priority dateJul 6, 2016
Publication dateMar 28, 2017
Grant dateMar 28, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: forming a multi-layer stack comprising a first dielectric layer and a second dielectric layer above the first dielectric layer; forming a trench through the second dielectric layer and into an upper portion of the first dielectric layer; filling the trench with a sacrificial material; forming, on the stack, a mask with an opening aligned above a segment of the sacrificial material; forming a sidewall spacer in the opening such that a surface of the segment remains exposed; etching a via hole that extends through the segment and a lower portion of the first dielectric layer; and, removing all materials from above the second dielectric layer and any remaining sacrificial material. 2. The method of claim 1 , further comprising filling the trench and the via hole with at least one conductive material to form a metal line and a via, respectively. 3. The method of claim 1 , the forming of the trench comprising performing a sidewall image transfer process. 4. The method of claim 1 , further comprising, before the filling of the trench with the sacrificial material, lining the trench with a protective liner. 5. The method of claim 1 , the sacrificial material comprising an organic dielectric material. 6. The method of claim 1 , the forming of the sidewall spacer comprising selectively adjusting a width of the sidewall spacer so as to selectively adjust a size of the via hole. 7. The method of claim 1 , the first dielectric layer comprising a porous dielectric material with a dielectric constant of less than 2.7, the second dielectric layer comprising a nitride layer and the mask comprising an oxide layer. 8. A method comprising: forming a multi-layer stack comprising a first dielectric layer and a second dielectric layer above the first dielectric layer; forming multiple parallel trenches through the second dielectric layer and into an upper portion of the first dielectric layer; filling the trenches with a sacrificial material; forming, on the stack, a mask with openings aligned above segments of the sacrificial material in the trenches; forming sidewall spacers in the openings such that, in each opening, a surface of a segment of the sacrificial material remains exposed; etching via holes that extend through the segments and a lower portion of the first dielectric layer; filling the via holes and the openings with the sacrificial material; performing a chemical mechanical polishing process to remove all materials from above the second dielectric layer; and, selectively removing any remaining sacrificial material from the trenches and the via holes. 9. The method of claim 8 , further comprising filling the trenches and the via holes with at least one conductive material to form metal lines and vias, respectively. 10. The method of claim 8 , the forming of the trenches comprising performing a sidewall image transfer process. 11. The method of claim 8 , further comprising, before the filling of the trenches with the sacrificial material, lining the trenches with a protective liner. 12. The method of claim 8 , the sacrificial material comprising an organic dielectric material. 13. The method of claim 8 , the forming of the sidewall spacers comprising selectively adjusting a width of the sidewall spacers so as to selectively adjust a size of the via holes. 14. The method of claim 8 , the first dielectric layer comprising a porous dielectric material with a dielectric constant of less than 2.7, the second dielectric layer comprising a nitride layer and the mask comprising an oxide layer. 15. A method comprising: forming a multi-layer stack comprising a first dielectric layer and a second dielectric layer above the first dielectric layer; forming multiple parallel trenches through the second dielectric layer and into an upper portion of the first dielectric layer; filling the trenches with a sacrificial material; forming, on the stack, a mask with an opening that traverses multiple ones of the trenches so as to be aligned above segments of the sacrificial material in the trenches; forming a sidewall spacer in the opening such that a surface of each of the segments of the sacrificial material remains exposed; etching via holes that extend through the segments and a lower portion of the first dielectric layer; filling the via holes and the opening with the sacrificial material; performing a chemical mechanical polishing process to remove all materials from above the second dielectric layer; and, selectively removing any remaining sacrificial material from the trenches and the via holes. 16. The method of claim 15 , further comprising filling the trenches and the via holes with at least one metal to form metal lines and vias, respectively. 17. The method of claim 15 , the forming of the trenches comprising performing a sidewall image transfer process. 18. The method of claim 15 , further comprising, before the filling of the trenches with the sacrificial material, lining the trenches with a protective liner. 19. The method of claim 15 , the sacrificial material comprising an organic dielectric material. 20. The method of claim 15 , the forming of the sidewall spacers comprising selectively adjusting a width of the sidewall spacer so as to selectively adjust a size of the via holes.

Assignees

Inventors

Classifications

  • by forming self-aligned vias · CPC title

  • characterised by the processes involved to create the masks · CPC title

  • using masks for insulating materials · CPC title

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

  • involving intermediate temporary filling with material · CPC title

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What does patent US9607893B1 cover?
Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and…
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 28 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).