Semiconductor device and method of forming thereof

Patent metadata

Field	Value
Publication number	US-9240374-B2
Application number	US-201314142934-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Dec 30, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate prepared with intermediate dielectric layer having interconnect levels. The interconnect levels include M 1 to M X metal levels, where 1 is the lowest level and X corresponds to a number of metal level. The metal level M X includes a metal pad having an oxidized portion. An upper level having an upper dielectric layer is formed over the dielectric layer having M X . The upper dielectric layer includes a plurality of via contacts over the metal pad and a metal line over the via contacts. The oxidized portion remains within the metal pad and prevents punch through between M X and its adjacent underlying metal level M X-1 .

First claim

What is claimed is:

1. A method for forming a device comprising:
providing a substrate prepared with intermediate dielectric layer having interconnect levels, wherein the interconnect levels include M 1 to M X metal levels, where 1 is the lowest level and X corresponds to a number of metal level, the metal level M X includes a metal pad having an oxidized portion which is formed by hillock in the metal pad which is exposed to an oxygen ambient; and
forming an upper level having an upper dielectric layer over the dielectric layer having M X , wherein the upper dielectric layer is processed to form a plurality of via openings over the metal pad and a metal line trench over the via openings, wherein the metal line trench is formed by
providing a patterned mask layer having a pattern corresponding to the metal line trench,
performing an etch to remove portions of the dielectric layer unprotected by the patterned mask,
performing a removal process to remove the patterned mask layer, wherein the removal process does not remove the oxidized portion of the metal pad, thereby preventing punch through between M X and its adjacent underlying metal level M X-1 .

2. The method of claim 1 wherein providing a patterned mask layer comprising:
providing a photoresist and a bottom anti-reflective coating (BARC) layer over the upper dielectric layer; and
patterning the photoresist layer to form the patterned mask layer.

3. The method of claim 2 wherein the removal process comprises:
performing a solvent clean to remove the photoresist;
performing an ashing process to remove the BARC layer; and
performing a dry clean to remove remaining particles and residues of the photoresist and BARC layer.

4. The method of claim 1 wherein the oxidized portion includes a protrusion that extends about a top surface of the metal pad.

5. The method of claim 1 wherein:
the upper level is the global interconnect level, wherein the metal line trench is a fat wire trench and the via openings accommodate fat wire via contacts; and
the metal level M X is the uppermost interconnect level of the intermediate dielectric layer.

6. A method for forming a device comprising:
providing a substrate prepared with intermediate dielectric layer having interconnect levels, wherein the interconnect levels include M 1 to M X metal levels, where 1 is the lowest level and X corresponds to a number of metal level, the metal level M X is the uppermost interconnect level of the intermediate dielectric layer and includes a metal pad having an oxidized portion; and
forming an upper level having an upper dielectric layer over the dielectric layer having M X , wherein the upper dielectric layer is processed to form a plurality of via openings which accommodate via contacts over the metal pad and a metal line trench over the via openings, wherein the upper level is the global interconnect level, the metal line trench is a fat wire trench and the via contacts are fat wire via contacts, and wherein the metal line trench is formed by
providing a patterned mask layer having a pattern corresponding to the metal line trench,
performing an etch to remove portions of the dielectric layer unprotected by the patterned mask,
performing a removal process to remove the patterned mask layer, wherein the removal process does not remove the oxidized portion of the metal pad, thereby preventing punch through between M X and its adjacent underlying metal level M X-1 .

7. A method for forming a device comprising:
providing a substrate prepared with intermediate dielectric layer having interconnect levels, wherein the interconnect levels include M 1 to M X metal levels, where 1 is the lowest level and X corresponds to a number of metal level, the metal level M X includes a metal pad having an oxidized portion, wherein the metal pad comprises Cu or Cu alloy and the oxidized portion is formed by Cu hillock within the metal pad which is exposed to an oxygen ambient during processing; and
forming an upper level having an upper dielectric layer over the dielectric layer having M X , wherein the upper dielectric layer comprises a plurality of via contacts over the metal pad and a metal line over the via contacts,
wherein the oxidized portion remains within the metal pad and prevents punch through between M X and its adjacent underlying metal level M X-1 .

8. The method of claim 7 wherein the plurality of via contacts and the metal line are formed by:
processing the upper dielectric layer to form a plurality of via openings over the metal pad and a metal line trench over the via openings; and
filling the via openings and metal line trench with a conductive material to form the via contacts and the metal line.

9. The method of claim 8 wherein the metal line trench is formed by:
providing a patterned mask layer having a pattern corresponding to the metal line trench;
performing an etch to remove portions of the dielectric layer unprotected by the patterned mask; and
performing a removal process to remove the patterned mask layer, wherein the removal process does not remove the oxidized portion of the metal pad, thereby preventing punch through between M X and its adjacent underlying metal level M X-1 .

10. The method of claim 9 wherein the removal process comprises performing a dry clean to remove remaining particles and residues of the patterned mask layer.

11. The method of claim 10 wherein the dry clean comprises an aerosol clean.

12. The method of claim 11 wherein the aerosol clean comprises gases having N 2 .

13. The method of claim 7 wherein:
the upper level is the global interconnect level, wherein the metal line is a fat wire and the via contacts are fat wire via contacts; and
the metal level M X is the uppermost interconnect level of the intermediate dielectric layer.

14. The method of claim 7 comprising forming an etch stop layer in between the dielectric layer having M X and the upper dielectric layer.

15. The method of claim 14 wherein:
the etch stop layer comprises a nitrogen doped SiC layer; and
the upper dielectric layer comprises a bottom and a top dielectric stack, wherein the bottom dielectric layer comprises TEOS and the top dielectric layer comprises FTEOS.

16. The method of claim 14 wherein the plurality of via contacts and the metal line are formed by:
processing the upper dielectric layer to form a plurality of via openings over the metal pad and a metal line trench over the via openings; and
filling the via openings and metal line trench with a conductive material to form the via contacts and metal line.

17. The method of claim 16 wherein the plurality of via openings over the metal pad are formed by a dry etch process.

18. The method of claim 17 wherein the dry etch process is selective to the etch stop layer.

19. The method of claim 17 wherein the oxidized portion is formed during and after the via openings formation by the dry etch process or exposed to chemical reaction during formation of the metal line trench.

20. The method of claim 14 wherein the oxidized portion includes a protrusion that extends above the etch stop layer.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Shao Wei
• Yi Wanbing
• Gong Shunqiang
• Zhu Chao
• Tan Juan Boon

Classifications

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/4405

  the principal metal being aluminium · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title