Interconnect structures with fully aligned vias

Patent metadata

Field	Value
Publication number	US-9324650-B2
Application number	US-201414460435-A
Country	US
Kind code	B2
Filing date	Aug 15, 2014
Priority date	Aug 15, 2014
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

A method of forming a fully aligned via connecting two metal lines on different Mx levels by forming a recessed opening above a first metal line in a first ILD; forming a cap on the first ILD and in the recessed openings; forming a second ILD on the cap; forming a metal trench hardmask above the second ILD, forming a metal trench pattern in the metal trench hardmask; forming a via pattern that is self aligned to the metal trench pattern and above a portion of the first metal line; forming a via opening exposing the first metal line by transferring the via pattern and metal trench pattern to lower levels, the via pattern is self-aligned to the recessed opening; and forming a via and a third metal line in the via opening and the transferred metal trench pattern, respectively.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a first metal line and a second metal line in a first inter-level dielectric (ILD);
forming a first recessed opening by recessing the first metal line below a top surface of the first ILD;
forming a cap on the first ILD and in the first recessed opening;
forming a second ILD on the cap;
forming a higher level hardmask on the second ILD;
forming a metal trench hardmask on the higher level hardmask;
forming a metal trench pattern in the metal trench hardmask, wherein a portion of the metal trench pattern is above a portion of the first recessed opening;
forming a via pattern material on the metal trench hardmask and in the metal trench pattern;
forming a first via pattern in the via pattern material, the first via pattern is located above a portion of the metal trench pattern and above the portion of the first recessed opening, wherein the first via pattern is self aligned to the metal trench pattern;
removing the via pattern material;
forming a first higher level trench in the higher level hardmask and in the second ILD, wherein the first higher level trench includes a first via opening, wherein the first via opening is the first via pattern transferred to a lower level; and
forming a third metal line and a first via in the first higher level trench and in the first via opening, respectively, wherein the via connects the first metal line to the third metal line.

2. The method of claim 1 , further comprising:
forming a trench stop hardmask between the first ILD and the cap.

3. The method of claim 1 , wherein the first ILD and the second ILD are the same material.

4. The method of claim 2 , wherein the first via opening is formed by etching the second ILD and the cap and using the trench stop hardmask as an etch stop.

5. The method of claim 2 , wherein the trench stop hardmask is a low-k silicon carbonitride with dielectric constant of 2.5-5.

6. The method of claim 1 , wherein the cap is conformally formed and the cap is a silicon nitride or silicon carbonitride.

7. The method of claim 1 , further comprising:
forming a second recessed opening by recessing the second metal line below the top surface of the first ILD;
forming a second via pattern in the via pattern material, the second via pattern is located above a portion of the metal trench pattern and above a portion of the second recessed opening, wherein the second via pattern is self aligned to the metal trench pattern;
forming a second higher level trench in the higher level hardmask and in the second ILD, wherein the second higher level trench includes a second via opening, wherein the second via opening is the second via pattern transferred to a lower level; and
forming a forth metal line and a second via in the second higher level trench and the second via opening, respectively, wherein the second via connects the second metal line to the fourth metal line.

Assignees

• IBM

Inventors

• Edelstein Daniel C
• Fuller Nicholas C
• Huang Elbert E
• Nitta Satyanarayana V
• Rath David L

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title