Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects

Patent metadata

Field	Value
Publication number	US-9236342-B2
Application number	US-201314133385-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Dec 18, 2013
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.

First claim

What is claimed is:

1. An interconnect structure for an integrated circuit, the interconnect structure comprising:
a first layer of the interconnect structure disposed above a substrate, the first layer comprising a first grating of alternating metal lines and dielectric lines in a first direction, wherein the dielectric lines have an uppermost surface higher than an uppermost surface of the alternating metal lines; and
a second layer of the interconnect structure disposed above the first layer of the interconnect structure, the second layer of the interconnect structure comprising a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction, wherein the dielectric lines have a lowermost surface lower than a lowermost surface of the alternating metal lines of the second grating, wherein the dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating; and
a region of dielectric material disposed between the alternating metal lines of the first grating and the alternating metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating, the region of dielectric material comprising a cross-linked photolyzable material.

2. The interconnect structure of claim 1 , further comprising:
a conductive via disposed between and coupling a metal line of the first grating to a metal line of the second grating, the conductive via in the same plane as the region of dielectric material.

3. The interconnect structure of claim 2 , wherein the conductive via has a center directly aligned with a center of the metal line of the first grating and with a center of the metal line of the second grating.

4. The interconnect structure of claim 1 , wherein the dielectric lines of the first grating comprise a first dielectric material, and the dielectric lines of the second grating comprise a second, different dielectric material, and wherein the first and second dielectric materials are different than the cross-linked photolyzable material.

5. The interconnect structure of claim 1 , wherein the dielectric lines of the first grating and the dielectric lines of the second grating comprise a same dielectric material different than the cross-linked photolyzable material.

6. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
providing a metallization structure comprising an alternating metal line and dielectric line first grating having a first direction, each dielectric line of the first grating having a top surface essentially co-planar with a top surface of each metal line;
recessing the metal lines of the first grating below the top surface of the dielectric lines of the first grating and to form recessed metal lines of the first grating;
forming an inter layer dielectric (ILD) layer above the dielectric lines and the recessed metal lines of the first grating, the ILD layer having a second grating in a second direction, perpendicular to the first direction, revealing portions of the recessed metal lines;
forming a plurality of photobuckets in all possible via locations above the recessed metal lines;
exposing, developing and removing fewer than all of the plurality of photobuckets to form one or more via openings; and, subsequently,
baking all remaining photobuckets;
forming metal lines above, and vias in a same plane as, the baked photobuckets.

7. The method of claim 6 , wherein forming the ILD layer comprises:
forming an unpatterned layer of the ILD layer material;
forming a hardmask layer above the ILD layer, the hardmask layer having a pattern of the second grating; and
etching the unpatterned layer of the ILD layer material to provide the pattern of the second grating for the ILD layer.

8. The method of claim 6 , wherein forming the plurality of photobuckets comprises forming a layer of photolyzable material, and wherein baking the remaining photobuckets comprises cross-linking the remaining photobuckets.

9. The method of claim 6 , wherein baking the remaining photobuckets comprises forming a permanent ILD material.

10. The method of claim 6 , wherein the dielectric lines of the first grating comprise a first dielectric material, and the ILD layer comprises a second, different dielectric material.

11. The method of claim 6 , wherein the dielectric lines of the first grating and the ILD layer comprise a same dielectric material.

12. The method of claim 6 , wherein exposing, developing and removing fewer than all of the plurality of photobuckets comprises exposing the fewer than all of the plurality of photobuckets to extreme ultra-violet (EUV) irradiation.

13. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
forming a first hardmask layer above an inter layer dielectric (ILD) material layer, the first hardmask layer and an upper portion of the inter layer dielectric (ILD) material layer having a first grating in a first direction;
forming a second hardmask layer above the inter layer dielectric (ILD) material layer and above the first hardmask layer, the second hardmask layer having a second grating in a second direction, perpendicular to the first direction;
forming a dielectric material in openings formed by the grating patterns of the first and second hardmask layers;
forming a first plurality of photobuckets on the dielectric material in openings;
exposing, developing and removing fewer than all of the first plurality of photobuckets to form one or more corresponding non-plug locations, wherein the remaining photobuckets define plug locations;
removing the portions of the dielectric material not protected by the remaining photobuckets;
forming a second plurality of photobuckets in all possible via regions;
exposing, developing and removing fewer than all of the second plurality of photobuckets to form one or more via openings;
etching the inter layer dielectric (ILD) material layer through one or more via openings to form corresponding via locations;
removing all remaining of the first and second pluralities of photobuckets;
removing the second hardmask layer; and
forming metal vias in corresponding of the one or more via locations and metal lines above the metal vias.

14. The method of claim 13 , wherein forming the second hardmask layer comprises forming a carbon-based hardmask layer, and wherein removing the second hardmask layer comprises using an ashing process.

15. The method of claim 13 , further comprising:
removing the first hardmask layer.

16. The method of claim 13 , wherein exposing, developing and removing fewer than all of the first plurality of photobuckets and fewer than all of the second plurality of photobuckets comprises exposing to extreme ultra-violet (EUV) irradiation.

17. A method of fabricating an interconnect structure for an integrated circuit, the method comprising:
forming a first hardmask layer above an inter layer dielectric (ILD) material layer, the first hardmask layer having a first grating in a first direction;
forming a second hardmask layer above the inter layer dielectric (ILD) material layer and interleaved with the first hardmask layer;
forming a hardmask cap layer above the first and second hardmask layers, the hardmask cap layer having a second grating in a second direction, perpendicular to the first direction;
patterning the first hardmask layer using the hardmask cap layer as a mas

Assignees

• Bristol Robert L
• Lin Kevin
• Singh Kanwal Jit
• Myers Alan M
• Schenker Richard E
• Intel Corp

Inventors

• Bristol Robert L
• Lin Kevin
• Singh Kanwal Jit
• Myers Alan M
• Schenker Richard E

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/48

  Insulating materials thereof · CPC title