Temperature independent resistor

Patent metadata

Field	Value
Publication number	US-9583240-B2
Application number	US-201414469012-A
Country	US
Kind code	B2
Filing date	Aug 26, 2014
Priority date	Aug 26, 2014
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

The present disclosure relates to a semiconductor structure comprising a positive temperature coefficient thermistor and a negative temperature coefficient thermistor, connected to each other in parallel by means of connecting elements which are configured such that the resistance resulting from the parallel connection is substantially stable in a predetermined temperature range, and to a corresponding manufacturing method.

First claim

What is claimed:

1. A method of manufacturing an integrated circuit product, comprising the steps of:
forming a positive temperature coefficient thermistor that comprises a first resistive region, wherein forming said positive temperature coefficient thermistor comprises forming a metal-containing layer and performing at least one patterning process to define said first resistive region from said metal-containing layer and to define a metal-containing gate structure for a transistor that comprises a portion of said metal-containing layer;
forming a negative temperature coefficient thermistor that comprises a second resistive region; and
forming a plurality of connecting elements connecting said first resistive region in parallel with said second resistive region.

2. The method of claim 1 , wherein forming said metal-containing layer comprises depositing at least one of TiN and TiAlN.

3. The method of claim 1 , wherein the step of forming said negative temperature coefficient thermistor comprises forming a silicon-containing semiconductor material layer and performing at least one patterning process to define said second resistive region from said silicon-containing semiconductor material layer and to define a portion of a gate structure for a transistor.

4. The method of claim 3 , wherein the step of forming said silicon-containing semiconductor material layer comprises depositing one of silicon, polysilicon or SiGe.

5. The method of claim 1 , wherein forming said plurality of connecting elements comprises depositing one of silicon, polysilicon, SiGe or Ge.

6. A method of manufacturing an integrated circuit product, comprising:
forming an isolation structure in a semiconductor substrate, said isolation structure being positioned between first and second regions of said substrate;
depositing a layer of insulating material above said first and second regions;
depositing a first metal-containing layer of material above said layer of insulating material and above said first and second regions;
depositing a semiconductor material layer above said first metal-containing layer of material and above said first and second regions;
forming a plurality of conductive contacts above said first region, said conductive contacts extending through said semiconductor material layer and contacting said first metal-containing layer of material positioned above said first region and contacting a remaining portion of said semiconductor material layer positioned above said first region; and
performing at least one process operation to pattern at least said semiconductor material layer, said first metal-containing layer of material and said layer of insulating material so as to define at least a portion of a gate structure of a transistor, said gate structure being positioned above said second region.

7. The method of claim 6 , wherein said first metal-containing layer of material positioned above said first region constitutes a first resistive region of a positive temperature coefficient thermistor and said remaining portion of said semiconductor material layer positioned above said first region constitutes a second resistive region of a negative temperature coefficient thermistor.

8. The method of claim 6 , wherein depositing said first metal-containing layer comprises depositing at least one of TiN and TiAlN.

9. The method of claim 8 , wherein depositing said semiconductor material layer comprises depositing one of silicon, polysilicon or SiGe.

10. The method of claim 9 , wherein forming said plurality of conductive contacts comprises depositing one of silicon, polysilicon, SiGe or Ge.

11. A method of manufacturing an integrated circuit product, comprising the steps of:
forming a positive temperature coefficient thermistor that comprises a first resistive region;
forming a negative temperature coefficient thermistor that comprises a second resistive region, wherein said negative temperature coefficient thermistor comprises forming a silicon-containing semiconductor material layer and performing at least one patterning process to define said second resistive region from said silicon-containing semiconductor material layer and to define a portion of a gate structure for a transistor; and
forming a plurality of connecting elements connecting said first resistive region in parallel with said second resistive region.

12. The method of claim 11 , wherein the step of forming said silicon-containing semiconductor material layer comprises depositing one of silicon, polysilicon or SiGe.

13. The method of claim 11 , wherein forming said plurality of connecting elements comprises depositing one of silicon, polysilicon, SiGe or Ge.

Assignees

• Globalfoundries Inc

Inventors

• Flachowsky Stefan
• Illgen Ralf
• Hoentschel Jan

Classifications

• H01C7/008

  Thermistors (H01C7/02 - H01C7/06 take precedence) · CPC title

• H01C7/021

  formed with two or more layers · CPC title

• H01C7/027

  consisting of conducting or semi-conducting material dispersed in a non-conductive organic material · CPC title

• H01C17/075

  by thin-film techniques · CPC title

• H01C1/16 Primary

  Resistor networks not otherwise provided for · CPC title