Method and apparatus for generating piece-wise linear regulated supply

Patent metadata

Field	Value
Publication number	US-9496007-B2
Application number	US-201414503545-A
Country	US
Kind code	B2
Filing date	Oct 1, 2014
Priority date	Oct 25, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that receives a reference voltage and an analog supply voltage. A second clamp circuit receives the reference voltage. A voltage divider circuit is coupled to the first clamp circuit and the second clamp circuit. The voltage divider circuit receives a peripheral supply voltage and generates a regulated supply voltage.

First claim

What is claimed is:

1. A voltage regulator comprising:
a first clamp circuit configured to receive a reference voltage and an analog supply voltage;
a second clamp circuit configured to receive the reference voltage, and
a voltage divider circuit coupled to the first clamp circuit and the second clamp circuit, the voltage divider circuit configured to receive a peripheral supply voltage and configured to generate a regulated supply voltage.

2. The voltage regulator of claim 1 , wherein the first clamp circuit comprises:
a first amplifier whose first terminal is configured to receive the reference voltage; and
a PMOS transistor whose source terminal is configured to receive the analog supply voltage and whose gate terminal is configured to receive an output of the first amplifier, wherein a second terminal of the first amplifier and a drain terminal of the PMOS transistor are coupled to a first node of the voltage divider circuit.

3. The voltage regulator of claim 1 , wherein the second clamp circuit comprises:
a second amplifier whose first terminal is configured to receive the reference voltage; and
an NMOS transistor whose source terminal is coupled to a ground terminal and whose gate terminal is configured to receive an output of the second amplifier, wherein a second terminal of the second amplifier and a drain terminal of the NMOS transistor are coupled to a second node of the voltage divider circuit.

4. The voltage regulator of claim 1 , wherein the voltage divider circuit comprises:
a first resistor configured to receive the peripheral supply voltage;
a second resistor coupled to the first resistor at the first node;
a third resistor coupled to the second resistor at the second node; and
a fourth resistor coupled to the third resistor at a third node, wherein the regulated supply voltage is generated at the third node.

5. The voltage regulator of claim 1 , wherein when the peripheral supply voltage is equal or below a first threshold voltage, the second clamp circuit is deactivated and the first clamp circuit is activated to maintain the first node at the reference voltage.

6. The voltage regulator of claim 1 , wherein when the peripheral supply voltage is above the first threshold voltage and below a second threshold voltage, the first clamp circuit and the second clamp circuit are deactivated such that the first node is above the reference voltage and the second node is below the reference voltage.

7. The voltage regulator of claim 6 , wherein the peripheral supply voltage is a ramp voltage between the first threshold voltage and the second threshold voltage, and the regulated supply voltage increases proportionately to the peripheral supply voltage such that the regulated supply voltage is a ramp voltage.

8. The voltage regulator of claim 1 , wherein when the peripheral supply voltage is equal or above the second threshold voltage, the first clamp circuit is deactivated and the second clamp circuit is activated to maintain the second node at the reference voltage.

9. A method of generating a regulated supply voltage comprising:
activating a first clamp circuit to maintain a first node of a voltage divider circuit at a reference voltage when a peripheral supply voltage is equal or below a first threshold voltage;
activating a second clamp circuit to maintain a second node of the voltage divider circuit at a reference voltage when the peripheral supply voltage is equal or above a second threshold voltage; and
deactivating the first clamp circuit and the second clamp circuit when the peripheral supply voltage is above the first threshold voltage and below the second threshold voltage.

10. The method of claim 9 further comprising:
deactivating the second clamp circuit when the peripheral supply voltage is equal or below the first threshold voltage; and
deactivating the first clamp circuit when the peripheral supply voltage is equal or above the first threshold voltage.

11. The method of claim 9 , wherein the first clamp circuit is coupled to a voltage divider circuit at a first node, and the second clamp circuit is coupled to the voltage divider circuit at a second node, the voltage divider circuit configured to receive the peripheral supply voltage.

12. The method of claim 9 , wherein when the peripheral supply voltage is above the first threshold voltage and below the second threshold voltage, the first node is above the reference voltage and the second node is below the reference voltage.

13. The method of claim 12 , wherein the peripheral supply voltage is a ramp voltage between the first threshold voltage and the second threshold voltage, and the regulated supply voltage increases proportionately to the peripheral supply voltage such that the regulated supply voltage is a ramp voltage.

14. The method of claim 9 further comprising generating the regulated supply voltage at a third node of the voltage divider circuit.

15. The method of claim 9 further comprising receiving the reference voltage by the first clamp circuit and the second clamp circuit, and receiving an analog supply voltage by the first clamp circuit.

16. A computing device comprising a processing unit, the processing unit further comprising:
a memory array; and
a voltage regulator coupled to the memory array, the voltage regulator comprising:
a first clamp circuit configured to receive a reference voltage and an analog supply voltage;
a second clamp circuit configured to receive the reference voltage, and
a voltage divider circuit coupled to the first clamp circuit and the second clamp circuit, the voltage divider circuit configured to receive a peripheral supply voltage and configured to generate a regulated supply voltage.

17. The computing device of claim 16 , wherein the first clamp circuit is coupled to the voltage divider circuit at a first node, and the second clamp circuit is coupled to the voltage divider circuit at a second node.

18. The computing device of claim 16 , wherein when the peripheral supply voltage is equal or below a first threshold voltage, the second clamp circuit is deactivated and the first clamp circuit is activated to maintain the first node at the reference voltage.

19. The computing device of claim 16 , wherein when the peripheral supply voltage is above the first threshold voltage and below a second threshold voltage, the first clamp circuit and the second clamp circuit are deactivated such that the first node is above the reference voltage and the second node is below the reference voltage.

20. The computing device of claim 16 , wherein when the peripheral supply voltage is equal or above the second threshold voltage, the first clamp circuit is deactivated and the second clamp circuit is activated to maintain the second node at the reference voltage.

Assignees

• Texas Instruments Inc

Inventors

• Seth Sumantra
• Roy Subrato
• Verma Deepak

Classifications

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• H01C1/16

  Resistor networks not otherwise provided for · CPC title