Trap rich layer for semiconductor devices

Patent metadata

Field	Value
Publication number	US-9570558-B2
Application number	US-201514855652-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Dec 24, 2010
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit, comprising:
forming a first active layer in a first semiconductor wafer, wherein the first active layer comprises a first active device layer and a first metallization layer;
creating a trap rich layer in a second semiconductor wafer;
bonding the second semiconductor wafer to the first semiconductor wafer to form a bonded structure;
forming a second active layer in the second semiconductor wafer, wherein the second active layer comprises a second active device layer and a second metallization layer; and
electrically interconnecting the first and second metallization layers, wherein the trap rich layer is between the first active device layer and the second active device layer in the bonded structure.

2. The method of claim 1 , wherein the forming of the second active layer is performed after the bonding.

3. The method of claim 1 , wherein the forming of the second active layer is performed before the bonding.

4. The method of claim 1 , wherein the forming comprises forming the first active device layer above an insulator layer in the first semiconductor wafer.

5. The method of claim 1 , wherein the forming of the second active layer comprises forming the second active device layer above an insulator layer in the second semiconductor wafer.

6. The method of claim 1 , further comprising providing a bonding layer on a bottom surface of the second semiconductor wafer; wherein the bonding comprises attaching the bonding layer to a top surface of the first semiconductor wafer.

7. The method of claim 6 , wherein electrically interconnecting the first and second metallization layers comprises creating a via through the bonding layer.

8. The method of claim 1 , wherein electrically interconnecting the first and second metallization layers comprises fabricating a metal contact for electrically coupling the first and second metallization layers.

9. The method of claim 8 , wherein the bonding comprises forming a first metal-to-metal bond between the metal contact and a metal surface of the first metallization layer and a second metal-to-metal bond between the metal contact and a metal surface of the second metallization layer.

10. The method of claim 1 , further comprising creating a trap rich layer in a third semiconductor wafer, and attaching the third semiconductor wafer to the bonded structure.

11. The method of claim 10 , wherein the third semiconductor wafer is bonded to a bottom surface of the first semiconductor wafer.

12. The method of claim 10 , wherein the third semiconductor wafer is bonded to a top surface of the second semiconductor wafer.

13. A method of fabricating an integrated circuit, comprising:
forming a first active layer in a first semiconductor wafer, wherein the first active layer comprises a first active device layer and a first metallization layer;
creating a trap rich layer in a second semiconductor wafer;
bonding the second semiconductor wafer to the first semiconductor wafer to form a bonded structure;
forming a second active layer in the second semiconductor wafer, wherein the second active layer comprises a second active device layer and a second metallization layer;
electrically interconnecting the first and second metallization layers; and
removing a portion of the second semiconductor wafer before the trap rich layer is created in the second semiconductor wafer.

14. An integrated circuit, comprising:
a first semiconductor substrate comprising a first active layer, wherein the first active layer comprises a first active device layer and a first metallization layer;
a second semiconductor substrate comprising a trap rich layer and a second active layer in the second semiconductor substrate, wherein the second active layer comprises a second active device layer and a second metallization layer;
a bond between the second semiconductor substrate and the first semiconductor substrate to form a bonded structure; and
an electrical interconnection between the first metallization layer and the second metallization layer in the bonded structure, wherein the trap rich layer is between the first active device layer and the second active device layer in the bonded structure.

15. The integrated circuit of claim 14 , wherein the electrical interconnection comprises a metal contact between the first and second metallization layers, a first metal-to-metal bond between the metal contact and a metal surface of the first metallization layer, and a second metal-to-metal bond between the metal contact and a metal surface of the second metallization layer.

16. The integrated circuit of claim 14 , wherein the first active device layer is above an insulator layer in the first semiconductor substrate, and the second active device layer is above an insulator layer in the second semiconductor substrate.

Assignees

• Qualcomm Inc

Inventors

• Brindle Christopher N
• Stuber Michael A
• Molin Stuart B

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P90/1914 Primary

  using bonding · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/3456

  Polycrystalline · CPC title