Mask read-only memory array, memory device, and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9559104-B2
Application number	US-201615059352-A
Country	US
Kind code	B2
Filing date	Mar 3, 2016
Priority date	Mar 31, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A mask read-only memory array is provided. The mask read-only memory array includes a semiconductor substrate having a surface; and a heavily doped layer formed on the surface of semiconductor substrate. The mask read-only memory array also includes a plurality of lightly doped discrete regions formed on the heavily doped layer, and a metal silicide layer formed on the lightly doped discrete regions. Wherein the metal silicide layer and the plurality of reverse type lightly doped discrete regions form a plurality of Schottky diode memory cells. Further, the mask read-only memory array includes conductive vias formed one a partial number of the plurality of Schottky diode memory cells for applying column selecting voltage to select certain memory cells.

First claim

What is claimed is:

1. A mask read-only memory array, comprising:
a semiconductor substrate having a surface;
a heavily doped layer formed on the surface of semiconductor substrate;
a plurality of lightly doped discrete regions formed on the heavily doped layer;
a metal silicide layer formed on the lightly doped discrete regions, wherein the metal silicide layer and the plurality of lightly doped discrete regions form a plurality of Schottky diode memory cells; and
conductive vias formed on a partial number of the plurality of Schottky diode memory cells for applying column selecting voltage to select certain memory cells.

2. The mask read-only memory array according to claim 1 , further comprising:
a lightly doped layer formed on the heavily doped layer, from which the plurality of lightly doped discrete regions are formed;
a plurality of deep trenches penetrating through the lightly doped layer, the heavily doped layer, and a pre-determined depth of the semiconductor substrate to electrically insulate the lightly doped layer and the heavily doped layer into a plurality of portions aligned in a row direction;
a plurality of shallow trenches penetrating through the lightly doped layer to divide the lightly doped layer into a plurality of portions aligned in a column direction;
a first insulation material filled in the plurality of deep trenches; and
a second insulation material filled in the plurality of shallow trenches,
wherein the plurality of shallow trenches and the plurality of deep trenches divide the lightly doped layer into the plurality of lightly doped discrete regions.

3. The mask read-only memory array according to claim 2 , further comprising:
an electrode region formed in each of the rows of portions of the lightly doped layer insulated by the deep trenches, configured for applying row selecting voltage to the row of portions of the lightly doped layer through a corresponding portion of the heavily doped layer.

4. The mask read-only memory array according to claim 2 , further comprising:
a heavily doped region formed on the side surfaces and the bottom surfaces of the plurality shallow trenches in the lightly doped layer,
wherein:
the heavily doped region extends from the side surfaces to the lightly doped layer and to the semiconductor substrate; and
a conductive type of the heavily doped region is different from a doping type of the lightly doped layer.

5. The mask read-only memory array according to claim 2 , further comprising:
a heavily doped region formed on the side surfaces and the bottom surfaces of the plurality deep trenches,
wherein:
a portion of the heavily doped region in the lightly doped layer extends from the side surfaces to the lightly doped layer;
a portion of the heavily doped region in the heavily doped layer extends from the side surfaces to the heavily doped layer;
a portion of the heavily doped region in the semiconductor substrate extends from the side surfaces and bottom surfaces to the semiconductor substrate; and
a conductive type of the heavily doped region is different from a doping type of the lightly doped layer.

6. The mask read-only memory array according to claim 2 , wherein:
the first insulation material include a top portion and a bottom portion;
the top portion is made of un-doped polysilicon; and
the bottom portion is made of silicon oxide.

7. The mask read-only memory array according to claim 2 , wherein:
the semiconductor substrate is P-type doped;
the lightly doped layer is N-type lightly doped; and
the heavily doped region is N-type heavily doped.

8. The mask read-only memory array according to claim 1 , wherein:
the metal silicide layer is made of one of NiSi, CoSi, PtSi, and TiSi; and
the conductive vias are made of one of W, Ti, and Ta.

9. A method for fabricating a mask read-only memory array, comprising:
providing a semiconductor substrate;
forming a heavily doped layer on the semiconductor substrate;
forming a plurality of lightly doped discrete regions on the heavily doped layer;
forming a metal silicide layer on the plurality of lightly doped discrete regions to form a plurality of Schottky diode memory cells with the plurality of lightly doped discrete regions; and
forming a conductive via on each of a partial number of the plurality of Schottky diode memory cells for applying column selecting voltage to select certain memory cells.

10. The method according to claim 9 , wherein forming the plurality of lightly doped discrete regions further comprises:
forming a plurality of deep trenches penetrating through the epitaxial layer, the heavily doped layer, and a pre-determined depth of semiconductor substrate along a row direction;
forming a first insulation material in the plurality of deep trenches;
forming a plurality of shallow trenches penetrating through the epitaxial layer along a column direction, wherein the plurality of shallow trenches and the plurality of deep trenches divide the epitaxial layer into a plurality of epitaxial discrete regions;
forming a second insulation material in the plurality of shallow trenches; and
treating the epitaxial layer into a lightly doped layer, wherein the plurality of epitaxial discrete regions are treated into the plurality of lightly doped discrete regions.

11. The method according to claim 10 , after forming the plurality of lightly doped discrete regions, further comprising:
forming an electrode region in each of rows of portions of the lightly doped layer insulated by the plurality of deep trenches.

12. The method according to claim 10 , wherein:
the heavily doped layer is N-type doped by an ion implantation process;
doping ions are As ions;
an implanting dose of the As ions are in a range of approximately 1.0e15 cm −2 ˜8.0e15 cm −2 ; and
an implanting energy is in a range of approximately 30 KeV˜80 KeV.

13. The method according to claim 10 , wherein:
the shallow trenches are perpendicular to the deep trenches.

14. The method according to claim 10 , before forming the first insulation material, further including:
forming a pad oxide layer on inner side surfaces of the deep trenches; and
forming a heavily doped region in the inner side surfaces of the deep trenches by a vertical ion implantation process and an inclining ion implantation process.

15. The method according to claim 10 , before forming the second insulation material, further including:
forming a pad oxide layer on inner side surfaces of the shallow trenches; and
forming a heavily doped region in the inner side surfaces of the shallow trenches by a vertical ion implantation process and an inclining ion implantation process.

16. The method according to claim 14 , wherein:
the heavily doped region is P-type doped;
doping ions of the heavily doped region are one of B ions and BF 2 ions;
a doping dosage of B ions is in a range of approximately 1.0e13 cm −2 ˜8.02e14 cm −2 ;
an implanting energy of B ions is in a range of approximately 5 KeV˜15 KeV;
an inclining angle of the B ions is in a range of approximately 0˜45°;
a doping dosage of BF 2 ions is in a range of approximately 1.0e13 cm −2 ˜8.02e14 cm −2 ;
an implanting energy of BF 2 ions is in a range of approximately 5 KeV˜15 KeV; and
an inclining angle of the BF 2 ions is in a range of approximately 0˜45°.

17. The method according to claim 14 , wherein forming the metal silicide layer further comprises:
performing a first high temperature process; and
performing a spike annealing process,
wherein:
a temperature of the first high temperature pr

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zhang Chao

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title