3D SRAM/ROM with several superimposed layers and reconfigurable by transistor rear biasing

Patent metadata

Field	Value
Publication number	US-10923191-B2
Application number	US-201916510263-A
Country	US
Kind code	B2
Filing date	Jul 12, 2019
Priority date	Jul 13, 2018
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A 3D microelectronic device is provided with several superimposed layers of components, with an upper layer including one or several memory cells having a SRAM structure and provided with a rear biasing electrode. The biasing of the rear biasing electrode is modified to switch the memory cells from a ROM operating mode to a SRAM operating mode.

First claim

The invention claimed is:

1. A microelectronic device provided with several superimposed layers of components and comprising:
a lower level provided with one or several components formed in at least one first semiconductive layer,
an upper layer comprising transistors having respective channel regions formed in at least one second semiconductor layer arranged above the first semiconductive layer,
a set of memory cells each provided with a first inverter and a second inverter cross-connected, the first inverter and the second inverter being connected to, and arranged between, a supply line and a ground line,
the first inverter and the second inverter respectively comprising at least one first transistor of a first type, N or P, and at least one second transistor of the first type N or P, belonging to said upper layer, each of said first and second transistors having a lower electrode located between the second semiconductor layer and the first semiconductive layer and coupled by capacitive coupling with a channel region located in the second semiconductor layer,
said memory cells of said set of memory cells being further connected to:
a first biasing line of one among the lower electrode of the first transistor and the lower electrode of the second transistor,
a second biasing line of the other among the lower electrode of the at least one first transistor and the lower electrode of the at least one second transistor,

wherein said set of memory cells belong to a row of cells, said row of cells comprising a first cell connected to said first biasing line and to said second biasing line by means of a first pair of vias, a second cell of said row of cells being connected to said first biasing line and to said second biasing line by means of a second pair of vias,
the device further comprising a circuit configured to, during an initialisation sequence:
during a first phase, apply a first potential and a second potential different from the first potential, respectively on said first biasing line and said second biasing line, and apply a voltage between said supply line and the ground line, in such a way as to impose on each cell of said set of memory cells a logical data having a value depending on the first and second biasing lines to which the lower electrode of a first transistor of the respective cell and the lower electrode of a second transistor of the respective cell are respectively connected,
then
during a second phase, apply the same potential on the first biasing line and the second biasing line, and maintain a voltage between said supply line and the ground line, in such a way as to retain the logical data and render the cells of said set of memory cells available for read and write access.

2. The microelectronic device according to claim 1 , wherein
at least one first cell of said set of memory cells has a first transistor with a lower electrode which is connected to the first biasing line and has a second transistor with a lower electrode which is connected to the second biasing line,
at least one second cell of said set of memory cells has a first transistor with a lower electrode which is connected to the second biasing line and having a second transistor with a lower electrode which is connected to the first biasing line, in such a way that during said initialisation sequence, a first logical data is imposed on the first cell, and a second logical data, complementary to the first logical data, is imposed on the second cell.

3. The microelectronic device according to claim 1 , wherein
the cells of said set of memory cells respectively comprise at least one third transistor and at least one fourth transistor, with the third transistor and the fourth transistor being of a second type, P or N, opposite the first type,
the third transistor and the fourth transistor of each cell of the set of memory cells belonging to said upper layer and each having a lower electrode located between the second semiconductor layer and the first semiconductive layer and coupled by capacitive coupling with a channel region located in the second semiconductor layer,
said cells of said set of memory cells being connected to:
at least one third biasing line connected to one among the lower electrode of the third transistor and the lower electrode of the fourth transistor,
at least one fourth biasing line connected to the other among the lower electrode of the third transistor and the lower electrode of the fourth transistor.

4. The microelectronic device according to claim 3 , said circuit being configured during said first phase of the initialisation sequence to:
apply a pair of different potentials, respectively on said third biasing line and said fourth biasing line, then
during the second phase apply the same potential on the third biasing line and the fourth biasing line.

5. The microelectronic device according to claim 1 , wherein the first transistor and the second transistor, are:
respectively, a first load transistor and a second load transistor of type P, or
respectively, a first conduction transistor and a second conduction transistor of type N.

6. The microelectronic device according to claim 5 , wherein
wherein the first transistor and the second transistor are respectively, a first load transistor and a second load transistor of the type P, the cells of said set of memory cells each including a first conduction transistor having a gate connected to a gate of the first load transistor and including a second conduction transistor having a gate connected to a gate of the second load transistor, with the first and second conduction transistors including respective lower electrodes coupled by capacitive coupling with a channel region, the lower electrodes respectively of said first conduction transistor and of said second conduction transistor being set to the same potential during the first phase of the initialisation sequence or being set respectively to a third potential and to a fourth potential, or
wherein the first transistor and the second transistor are respectively, a first conduction transistor and a second conduction transistor of the type N, the cells of said set of memory cells each including a first load transistor having a gate connected to a gate of the first conduction transistor and including a second load transistor having a gate connected to a gate of the second conduction transistor, with the first and second conduction transistors including respective lower electrodes coupled by capacitive coupling with a channel region, the lower electrodes respectively of said first load transistor and of said second load transistor being, during the first phase of the initialisation sequence, set to the same potential or being set respectively to a third potential and to a fourth potential.

7. The microelectronic device according to claim 6 , wherein said cells of said set of memory cells are further provided with a first access transistor to a first node and with a second access transistor to a second node, with the first access transistor and the second access transistor each being provided with respective lower electrodes located between the second semiconductor layer and the first semiconductive layer and coupled by capacitive coupling with a channel region located in the second semiconductor layer.

8. The microelectronic device according to claim 7 , wherein the first and second access transistors are of the same type as the first transistor and the second transistor, with the lower electrodes respectively of said first access transistor and of said second access transistor being, during the first phase of the initialisation sequence, set to the same potential or being set respectively to the first potential and to the second p

Assignees

• Commissariat Energie Atomique

Inventors

• Coriat David
• Makosiej Adam

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title