Integrated circuit devices and fabrication techniques

Patent metadata

Field	Value
Publication number	US-10937811-B2
Application number	US-201916412357-A
Country	US
Kind code	B2
Filing date	May 14, 2019
Priority date	Apr 4, 2013
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

First claim

The invention claimed is:

1. A device, comprising:
a substrate;
a fin extending from a first surface of the substrate and having a fin height;
a source extending from the first surface of the substrate;
a drain extending from the first surface of the substrate, the fin extending between the source and drain on the first surface of the substrate; and
a gate structure, including:
a first portion extending from the first surface of the substrate to a gate height that is greater than the fin height, the first portion being adjacent to a first side of the fin;
a second portion extending from the first surface of the substrate to the gate height, the second portion being adjacent to a second side of the fin that is opposite to the first side, and the first portion being spaced apart from the second portion; and
a third dielectric portion that is between the first portion and the second portion and extends to the gate height, a first part of the third portion between the first side of the fin and the first portion of the gate structure, a second part of the third portion between the second side of the fin and the second portion of the gate structure, and a third part of the third portion extending from a surface of the fin at the fin height to the gate height and separating the first portion of the gate structure from the second portion of the gate structure.

2. The device of claim 1 , wherein the first portion and the second portion are laterally positioned relative to a channel in the fin, and are aligned in a transverse orientation with respect to a length of the fin between the source and the drain.

3. The device of claim 1 , wherein the source, the drain, and the fin are portions of a single contiguous layer.

4. The device of claim 1 , wherein the source, the drain, and the fin are portions of a single contiguous layer.

5. A method, comprising:
doping a first portion of a substrate corresponding to a source region while also doping a second portion of the substrate corresponding to a drain region while also doping a third portion of the substrate corresponding to a via contact;
forming a fin structure of a semiconductor device, the fin structure extending outward from a first surface of the substrate to a fin height and between the source region and the drain region; and
forming a gate and a local interconnect of the semiconductor device, the gate and the local interconnect being a same material, forming the gate including:
forming a first portion extending from the first surface of the substrate to a gate height that is greater than the fin height, the first portion being adjacent to a first side of the fin;
forming a second portion extending from the first surface of the substrate to the gate height, the second portion being adjacent to a second side of the fin that is opposite to the first side, and the first portion being spaced apart from the second portion; and
forming a third dielectric portion between the first portion and the second portion and extending to the gate height, a first part of the third portion between the first side of the fin and the first portion of the gate, a second part of the third portion between the second side of the fin and the second portion of the gate, and a third part of the third portion extending from a surface of the fin at the fin height to the gate height and separating the first portion of the gate from the second portion of the gate”.

6. The method of claim 5 , wherein the doping includes:
forming a first mask over the substrate;
removing the first mask over the first portion, the second portion, and the third portion of the substrate; and
implanting dopants into the first portion, the second portion, and the third portion of the substrate.

7. The method of claim 6 , wherein a portion of the substrate corresponding to a channel is fully or partially depleted.

8. The method of claim 6 , wherein forming the fin structure includes:
forming openings in the first mask over an area of the substrate corresponding to the fin structure of the semiconductor device;
forming a second mask in the openings in the first mask;
removing the first mask; and
removing portions of the substrate exposed by removing the first mask.

9. The method of claim 8 , wherein the fin structure is a single contiguous layer and includes the source region, the drain region, and a channel.

10. The method of claim 5 , wherein forming the gate is after forming the fin structure of the semiconductor device.

11. The method of claim 5 , wherein forming the gate and the local interconnect includes:
forming a conductive layer on the substrate and the fin structure; and
forming the gate and the local interconnect from the conductive layer.

12. A device, comprising:
a substrate having a surface;
a fin extending from the surface of the substrate to a first height;
a source extending from the surface of the substrate to the first height;
a drain extending from the surface of the substrate to the first height, the fin extending between and abutting the source and the drain on the surface of the substrate; and
a gate structure, including:
a first portion extending from the surface of the substrate to a second height that is greater than the first height, the first portion being adjacent to a first side of the fin; and
a second portion extending from the surface of the substrate to the second height, the second portion being adjacent to a second side of the fin that is opposite to the first side, and the first portion being spaced apart and separated from the second portion, wherein:
the first portion of the gate structure has a surface that extends from the surface of the substrate to the second height, and the fin has a first surface that extends from the surface of the substrate to the first height, the first surface of the fin facing the surface of the first portion of the gate structure;
the second portion of the gate structure has a surface that extends from the surface of the substrate to the second height, and the fin has a second surface that extends from the surface of the substrate to the first height, the second surface of the fin facing the surface of the second portion of the gate structure;
the gate structure further includes a third portion that is arranged between the surface of the first portion of the gate structure and the surface of the second portion of the gate structure and extends to the second height, the third portion of the gate structure being a dielectric; and
a first part of the third portion of the gate structure is arranged between the first surface of the fin and the surface of the first portion of the gate structure, a second part of the third portion of the gate structure is arranged between the second surface of the fin and the surface of the second portion of the gate structure, and a third part of the third portion of the gate structure extending from a surface of the fin at the first height to the second height and separating the first portion of the gate structure from the second portion of the gate structure.

13. The device of claim 12 , further including a channel in the fin, the channel being arranged between the first portion and the second portion of the gate structure.

14. The device of claim 12 , wherein the gate structure, source, and drain extend in a first direction and the fin extends in a second direction that is transverse to the first direction.

15. The device of claim 12 , wherein the source, the drain, and the fin are portions of a single contiguous layer.

Assignees

• St Microelectronics Inc

Inventors

• Zhang John H

Classifications

• H10P30/22

  using masks · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10D86/011 Primary

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title