Apparatus for high speed ROM cells

Patent metadata

Field	Value
Publication number	US-10658010-B2
Application number	US-201816229072-A
Country	US
Kind code	B2
Filing date	Dec 21, 2018
Priority date	Mar 30, 2012
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

An apparatus comprises a plurality of memory cells in rows and columns, a first word line electrically coupled to a first group of memory cells through a first word line strap structure comprising a first gate contact, a first-level via, a first metal line and a second-level via and a second word line electrically coupled to a second group of memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.

First claim

What is claimed is:

1. An apparatus comprising:
a first bit line in a first interconnect layer over a substrate;
a second bit line in the first interconnect layer;
a first electrical ground line (VSS line) in a first contact layer between the substrate and the first interconnect layer;
a second VSS line in the first interconnect layer, the second VSS line extending perpendicularly to the first VSS line and coupled to the first VSS line;
first memory cells in a first row, each of the first memory cells comprising:
a first transistor in the substrate, wherein a source of the first transistor is coupled to the first VSS line, and a drain of the first transistor is couple to the first bit line or to the second bit line;

a first word line in a second interconnect layer over the first interconnect layer and electrically coupled to a gate of the first transistor of each of the first memory cells through a first word line strap structure, the first word line strap structure comprising a first gate contact in the first contact layer, a first-level via in the first interconnect layer, a first metal line in the first interconnect layer, and a second-level via in the second interconnect layer;
second memory cells in a second row adjacent and parallel to the first memory cells; and
a second word line in the second interconnect layer and electrically coupled to the second memory cells through a second word line strap structure, wherein the second word line strap structure and the first word line strap structure are separated by at least two memory cells.

2. The apparatus of claim 1 , wherein the each of the second memory cells comprises:
a second transistor in the substrate, wherein a source of the second transistor is coupled to the first VSS line, a drain of the second transistor is coupled to the first bit line or to the second bit line, and a gate of the second transistor is coupled to the second word line through the second word line strap structure.

3. The apparatus of claim 2 , wherein the first memory cells in the first row and the second memory cells in the second row define a rectangular area, wherein the first word line strap structure and the second word line strap structure are disposed along a diagonal line of the rectangular area.

4. The apparatus of claim 2 , further comprising a row of isolation transistors between the first memory cells in the first row and the second memory cells in the second row, wherein each isolation transistor of the row of isolation transistors is coupled between a respective first transistor and a respective second transistor, wherein the each isolation transistor comprises:
a source coupled to the drain of the respective first transistor;
a drain coupled to the drain of the respective second transistor; and
a gate coupled to the first VSS line.

5. The apparatus of claim 1 , wherein the first memory cells and the second memory cells are read only memory (ROM) cells.

6. The apparatus of claim 1 , wherein:
the first word line is electrically coupled to four first memory cells, wherein the four first memory cells are horizontally adjacent to each other; and
the second word line is electrically coupled to four second memory cells, wherein the four second memory cells are horizontally adjacent to each other, and wherein the first row is vertically adjacent to the second row, and wherein:
the first memory cells and the second memory cells form a rectangle; and
the first word line strap structure and the second word line strap structure are placed diagonally in the rectangle.

7. The apparatus of claim 6 , wherein:
the first word line strap structure is between a first memory cell and a second memory cell of the first row; and
the second word line strap structure is between a third memory cell and a fourth memory cell of the second row.

8. The apparatus of claim 1 , wherein:
the first word line is electrically coupled to eight first memory cells, wherein the eight first memory cells are horizontally adjacent to each other; and
the second word line is electrically coupled to eight second memory cells, wherein the eight second memory cells are horizontally adjacent to each other, and wherein the first row is vertically adjacent to the second row, and wherein:
the first memory cells and the second memory cells form a rectangle; and
the first word line strap structure and the second word line strap structure are placed diagonally in the rectangle.

9. The apparatus of claim 8 , wherein:
the first word line strap structure is between a first memory cell and a second memory cell of the first row; and
the second word line strap structure is between a seventh memory cell and an eighth memory cell of the second row.

10. An apparatus comprising:
a first memory cell comprising a first pass transistor;
a second memory cell comprising a second pass transistor;
a first bit line over the first memory cell and the second memory cell;
a second bit line over the first memory cell and the second memory cell, wherein a first drain of the first pass transistor is coupled to the first bit line or the second bit line, and a second drain of the second pass transistor is coupled to the first bit line or the second bit line;
a first word line, wherein a first gate of the first pass transistor is coupled to the first word line;
a second word line, wherein a second gate of the second pass transistor is coupled to the second word line, wherein a source of the first pass transistor is coupled to a first electrical ground line (VSS line), and a source of the second pass transistor is coupled to the first VSS line, wherein the first VSS line is disposed in a first dielectric layer over a substrate, the first bit line and the second bit line are disposed in a second dielectric layer over the first dielectric layer, and the first word line and the second word line are disposed in a third dielectric layer over the second dielectric layer; and
an isolation transistor coupled between the first pass transistor and the second pass transistor, wherein a source of the isolation transistor is coupled to the first drain of the first pass transistor, a drain of the isolation transistor is coupled to the second drain of the second pass transistor, and a gate of the isolation transistor is coupled to electrical ground.

11. The apparatus of claim 10 , wherein the isolation transistor is configured to stay in an OFF state.

12. The apparatus of claim 10 , wherein the first pass transistor, the second pass transistor, and the isolation transistor are N-type transistors.

13. An apparatus comprising:
a first word line extending along a first direction;
a second word line extending along the first direction;
a first bit line extending along a second direction perpendicular to the first direction;
a second bit line extending along the second direction;
a first row of memory cells extending along the first direction, each of the first row of memory cells comprising a first transistor, wherein a first source of the first transistor is coupled to a first electrical ground line (VSS line), a first drain of the first transistor is coupled to the first bit line or the second bit line, and a first gate of the first transistor is coupled to the first word line, wherein the first VSS line is in a first contact layer over a substrate of the apparatus, wherein the first bit line and the second bit line are in a first interconnect layer over the first contact layer, and wherein the first word line and the second word line are in a second interconnect layer over the first interconnect layer;
a second row of memory cells adjacent to the first row of me

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon-Jhy

Classifications

• G11C17/08

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C17/12

  using field-effect devices · CPC title