Method of fabricating a memory device having multiple metal interconnect lines

Patent metadata

Field	Value
Publication number	US-11145599-B2
Application number	US-201916723323-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Jun 30, 2016
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.

First claim

What is claimed is:

1. A method of forming a memory device comprising:
providing a substrate having a pass-gate transistor in a first region and control circuitry in a peripheral region;
forming a first conductive via extending from a drain region of the transistor;
depositing a first metal line above the transistor, wherein the first metal line is operable to carry a first bit-line signal to the drain region via the first conductive via;
forming a second conductive via extending above and connected to the first metal line;
after depositing the first metal line, depositing a second metal line connected to the first metal line through the second conductive via; and
wherein at least one of the first and second metal lines extends to the control circuitry for the memory device;
depositing a third metal line;
forming a third conductive via to a gate of the transistor, wherein the third conductive via is electrically connected to the third metal line; and
depositing a fourth metal line, wherein the fourth metal line is connected to the third metal line by a fourth conductive via, wherein one of the third or fourth metal lines extends to the control circuitry for the memory device.

2. The method of forming the memory device of claim 1 , wherein the second conductive via is formed after the first metal line and prior to the second metal line.

3. The method of forming the memory device of claim 1 , further comprising:
sending a word line signal on the third metal line and the fourth metal line.

4. The method of forming the memory device of claim 1 , further comprising:
forming an inter-layer dielectric (ILD) layer between the third metal line and the fourth metal line.

5. The method of forming the memory device of claim 1 , wherein the second conductive via and one of the first metal line or the second metal line are formed in a damascene process.

6. The method of forming the memory device of claim 1 , further comprising:
sending a same signal on the first metal line and the second metal line.

7. A method of providing a memory device comprising:
forming a transistor having a gate structure interposing a drain region and a source region, wherein the gate structure on a semiconductor substrate;
depositing a first metal line of a first metal layer of a multi-layer interconnect (MLI) structure, wherein the first metal line extends horizontally on the first metal layer and is connected to the drain region;
forming a first conductive via connected to and extending above the first metal line;
depositing a landing pad above the first conductive via, wherein the landing pad is disposed on a second metal layer of the MLI structure;
forming a second conductive via connected to and extending above the landing pad;
depositing a second metal line above and connected to the second conductive via, the second metal line extending horizontally on a third metal layer of the MLI structure; and
providing a signal to/from the drain region on each of the first metal line and the second metal line to control circuitry.

8. The method of claim 7 ,
wherein the first conductive via and the second conductive via are vertically aligned.

9. The method of claim 7 , further comprising:
depositing an inter-layer dielectric (ILD) between the first metal layer and the second metal layer, wherein the ILD surrounds four sides of the landing pad having a rectangular shape.

10. The method of claim 7 ,
wherein the first metal line and the second metal line extend in a same direction, the second metal line being directly over the first metal line.

11. The method of claim 7 , further comprising:
forming a third metal line coplanar with the landing pad, wherein the third metal line is coupled to the transistor.

12. A method of forming a memory device comprising:
providing a substrate having a transistor in a first region and control circuitry in a peripheral region;
forming a first via extending from a drain region of the transistor;
depositing a first metal line above the first via, wherein the first metal line is operable to carry a first bit-line signal to the drain region via the first via;
forming a second via extending above and connected to the first metal line;
after depositing the first metal line, depositing a second metal line connected to the second conductive via, wherein at least one of the first metal line or the second metal line extends to the control circuitry for the memory device;
forming a third metal line electrically connected to a gate of the transistor; and
forming a fourth metal line, wherein the fourth metal line is connected to the third metal line by a third via, wherein one of the third or fourth metal lines extends to the control circuitry for the memory device.

13. The method of claim 12 , wherein the forming the first metal line includes depositing conductive material into patterned openings in a dielectric material.

14. The method of claim 12 , wherein depositing the first metal line includes depositing copper.

15. The method of claim 12 , further comprising: preparing a layout of the memory device such that a read or write operation of a memory cell comprising the transistor provides the first metal line and the second metal line at a same state and the third metal line and the fourth metal line at a same state.

16. The method of claim 12 , wherein the forming the third metal line forms the third metal line above the first metal line and below the second metal line.

17. The method of claim 16 , wherein the forming the fourth metal line includes forming the fourth metal line above the second metal line.

18. The method of claim 12 , further comprising: forming a fourth metal line, wherein the fourth metal line is above the second metal line, the fourth metal line coupled to the third metal line.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L27/1104

  Electricity · mapped topic