Ferroelectric devices including a layer having two or more stable configurations

US9536975B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9536975-B2
Application numberUS-201514745457-A
CountryUS
Kind codeB2
Filing dateJun 21, 2015
Priority dateSep 29, 2009
Publication dateJan 3, 2017
Grant dateJan 3, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is not ferroelectric in bulk but can be considered to be when the thickness is sufficiently reduced down to a few atomic layers. Devices including such ferroelectric layers are suitable for various applications, such as transistors and memory cells (both volatile and non-volatile).

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of ferroelectric switching, the method comprising: providing a semiconductor substrate; providing a ferroelectric layer of a material disposed on or above said substrate; wherein said ferroelectric layer has at least two stable configurations having different electrical polarizations; switching said ferroelectric layer between said stable configurations with an applied electric field; wherein said material does not exhibit bulk ferroelectricity; and wherein said ferroelectric layer is a single layer of lattice unit cells. 2. The method of claim 1 , wherein said substrate comprises silicon or germanium. 3. The method of claim 1 , wherein said material has a composition MX 2 . 4. The method of claim 3 , wherein said composition MX 2 has M selected from the group consisting of Zr, Hf, Ce, Ca, Pt, Pd, Rh, Ir, Ti, Fe, Ni, Co and V, and has X selected from the group consisting of O, F, S, As and P. 5. The method of claim 4 , wherein said ferroelectric layer comprises a material selected from the group consisting of: zirconium oxide, hafnium oxide, calcium fluoride, cerium oxide and mixtures thereof. 6. The method of claim 1 , wherein said ferroelectric layer is disposed on said substrate and wherein an insulator is disposed on a surface of said ferroelectric layer opposite said substrate. 7. The method of claim 6 , wherein said insulator comprises a material selected from the group consisting of lead titanate, barium titanate, strontium titanate, and alloys or mixtures thereof. 8. The method of claim 7 , wherein said insulator comprises strontium titanate. 9. The method of claim 6 , wherein said insulator comprises a material that does not exhibit bulk ferroelectricity, but is ferroelectric when substantially matched in size and symmetry to said substrate. 10. The method of claim 6 , wherein said insulator comprises a material that is not ferroelectric. 11. The method of claim 6 , wherein said insulator is amorphous. 12. The method of claim 1 , wherein an insulating layer stack is disposed on said substrate, wherein said ferroelectric layer is one of the layers of said insulating layer stack.

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Classifications

  • IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

  • H10B51/00Primary

    Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors · CPC title

  • comprising ferroelectric layers · CPC title

  • H10D64/689Primary

    having ferroelectric layers · CPC title

  • Electricity · mapped topic

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What does patent US9536975B2 cover?
Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is n…
Who is the assignee on this patent?
Univ Yale
What technology area does this patent fall under?
Primary CPC classification H10B51/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).