Variable resistance memory devices and methods of manufacturing the same
US-2015340610-A1 · Nov 26, 2015 · US
Semiconductor devices and methods of manufacturing the same
US2016148977A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016148977-A1 |
| Application number | US-201514980247-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 28, 2015 |
| Priority date | Nov 12, 2013 |
| Publication date | May 26, 2016 |
| Grant date | — |
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- Title
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Abstract
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A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of opposite sides of the variable resistance layer pattern. The second protective layer pattern is formed on a second pair of opposite of the variable resistance layer pattern. The second electrode is disposed on the variable resistance layer pattern.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method of manufacturing a semiconductor device, comprising: forming a first electrode layer, a selection device layer and a variable resistance layer sequentially on a substrate; selectively etching the variable resistance layer to form preliminary variable resistance layer patterns each extending longitudinally in a first direction; forming a first protective layer along sides of the preliminary variable resistance layer patterns, and a top surface of the selection device layer; etching portions of the first protective layer, the selection device layer and the first electrode layer situated between the preliminary variable resistance layer patterns to form first protective layer patterns, preliminary selection device patterns and first electrodes; forming a second electrode layer on the preliminary variable resistance layer patterns; selectively etching the second electrode layer and the preliminary variable resistance layer patterns to form second electrodes and variable resistance layer patterns, the second electrodes each extending longitudinally in a second direction that crosses the first direction; forming a second protective layer along side surfaces of the second electrodes, sides the variable resistance layer patterns, and sides of the preliminary selection device patterns; and etching portions of the second protective layer and the preliminary selection device patterns situated between the variable resistance layer patterns to form second protective layer patterns and selection device patterns. 2 . The method of claim 1 , wherein the first protective layer and the second protective layer are formed of silicon nitride or aluminum oxide. 3 . The method of claim 1 , further comprising: forming a third protective layer that covers side surfaces of the first protective layer pattern, sides of the selection device pattern, and side surfaces of the first electrode coplanar with the side surfaces of the first protective layer pattern; and forming a protective layer that covers side surfaces of the second protective layer pattern and sides of the selection device pattern which are coplanar with the side surfaces of the second protective layer pattern. 4 . The method of claim 1 , further comprising forming at least one metal layer on the selection device layer before the variable resistance layer is formed.
Assignees
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Classifications
Electricity · mapped topic
- H01L27/2409Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2016148977A1 cover?
- A semiconductor device includes a first electrode on a substrate, a selection device pattern, a variable resistance layer pattern, a first protective layer pattern, a second protective layer pattern and a second electrode. The selection device pattern is wider, in a given direction, than the variable resistance layer pattern. The first protective layer pattern is formed on a first pair of oppos…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H01L27/2409. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu May 26 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).