Electronic device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9443909-B2
Application number	US-201414229588-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Nov 7, 2013
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

An electronic device including a semiconductor memory includes a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate.

First claim

What is claimed is:

1. An electronic device including a semiconductor memory unit, the semiconductor memory unit comprising: a plurality of first electrodes and a plurality of second electrodes, which are disposed over a substrate and alternately arrayed in a first direction that is parallel to a plane of the substrate; and a plurality of resistance variable patterns, each of which is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, wherein the first and second electrodes and the resistance variable patterns extend upwards by a predetermined height from the substrate; wherein the semiconductor memory unit comprises a plurality of cell structures arrayed in a second direction crossing the first direction, each of the cell structures including first electrodes, second electrodes, and resistance variable patterns that are arrayed in the first direction, wherein each of the first electrodes, the second electrodes, and the resistance variable patterns in each of the cell structures are arrayed in rows in the second direction, and wherein the semiconductor memory unit further comprises: first lines extending in the first direction, each of the first lines being electrically coupled to corresponding first electrodes that are disposed in a corresponding cell structure and arrayed in the first direction: and second lines extending in the second direction, each of the second lines being electrically coupled to corresponding second electrodes that are disposed in the cell structures and arrayed in the second direction, and wherein when the first lines are over the cell structures the second lines are under the cell structures, and when the first lines are under the cell structures the second lines are over the cell structures.

2. The electronic device according to claim 1 , wherein upper surfaces of the plurality of first electrodes, the plurality of resistance variable patterns, and the plurality of second electrodes are disposed at substantially the same level over the substrate, and
wherein lower surfaces of the plurality of first electrodes and the plurality of resistance variable patterns are disposed at a level that is provided below lower surfaces of the plurality of second electrodes.

3. The electronic device according to claim 2 , further comprising:
insulation patterns, each of which is disposed between a corresponding one of the plurality of second electrodes and the substrate.

4. The electronic device according to claim 3 , wherein each of the plurality of resistance variable patterns includes a plurality of layers,
wherein the plurality of layers, in combination, have resistance variable characteristics,
wherein, in each of the plurality of resistance variable patterns, lowermost portions of layers that are not in contact with the corresponding one of the plurality of second electrodes among the plurality of layers have a bent portion that extends toward the corresponding second electrode in a direction parallel to the plane of the substrate, and
wherein a corresponding one of the insulation patterns has a top surface disposed over the lowermost portions of the layers that are not in contact with the corresponding one of the plurality of second electrodes.

5. The electronic device according to claim 3 , wherein the semiconductor memory unit comprises a plurality of stack structures including first and second stack structures that are vertically stacked over the substrate, each of the stack structures including a plurality of cell structures arrayed in a second direction crossing the first direction, each of the cell structures including first electrodes, second electrodes, first insulation patterns under the second electrodes, and resistance variable patterns that are arrayed in the first direction.

6. The electronic device according to claim 5 , wherein the first electrodes of the first stack structure are aligned with the second electrodes of the second stack structure so that the first electrodes of the first stack structure are parallel to and overlap with the second electrodes of the second stack structure, and
wherein the second electrodes of the first stack structure are aligned with the first electrodes of the second stack structure so that the second electrodes of the first stack structure are parallel to and overlap with the first electrodes of the second stack structure.

7. The electronic device according to claim 6 , wherein the semiconductor memory unit further comprises:
first lines extending in the first direction under the first stack structure, each of the first lines being electrically coupled to corresponding first electrodes that are disposed in a corresponding cell structure included in the first stack structure and arrayed in the first direction;
second lines extending in the second direction between the first stack structure and the second stack structure, each of the second lines being electrically coupled to corresponding second electrodes, which are disposed in the cell structures included in the first stack structure and arrayed in the second direction, and corresponding first electrodes, which are disposed in the cell structures included in the second stack structure and arrayed in the second direction; and
third lines extending in the first direction over the second stack structure, each of the third lines being electrically coupled to corresponding second electrodes that are disposed in a corresponding cell structure included in the second stack structure and arrayed in the first direction.

8. The electronic device according to claim 6 , wherein the semiconductor memory unit further comprises:
first lines extending in the second direction under the first stack structure, each of the first lines being electrically coupled to corresponding first electrodes that are disposed in the cell structures included in the first stack structure and arrayed in the second direction;
second lines extending in the first direction between the first stack structure and the second stack structure, each of the second lines being electrically coupled to corresponding second electrodes, which are disposed in a corresponding cell structure included in the first stack structure and arrayed in the first direction, and corresponding first electrodes, which are disposed a corresponding cell structure included in the second stack structure and arrayed in the first direction; and
third lines extending in the second direction over the second stack structure, each of the third lines being electrically coupled to corresponding second electrodes that are disposed in the cell structures included in the second stack structure and arrayed in the second direction.

9. The electronic device according to claim 1 , wherein each of the plurality of resistance variable patterns includes an oxygen-rich metal oxide layer and an oxygen-deficient metal oxide layer, which are laterally stacked over the substrate between the corresponding one of the plurality of first electrodes and the corresponding one of the plurality of second electrodes.

10. The electronic device according to claim 1 , wherein upper surfaces of the first electrodes, the resistance variable patterns and the second electrodes are disposed at substantially the same level, and
wherein lower surfaces of the first electrodes, the resistance variable patterns and the second electrodes are disposed at substantially the same level.

11. The electronic device according to claim 1 , wherein the semiconductor memory unit comprises a plurality of stack structures including first and second stack structures that are vertically stacked over the substrate, each of the stack structures including a

Assignees

• Sk Hynix Inc

Inventors

• Lee Dong-Hyeon

Classifications

• H01L45/147

  Electricity · mapped topic

• H01L45/04

  Electricity · mapped topic

• H01L27/2463

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/16

  Electricity · mapped topic