Vertical memory devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9431418-B2
Application number	US-201514697655-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Jun 23, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A vertical memory device and a method of manufacturing a vertical memory device are disclosed. The vertical memory device includes a substrate, a plurality of channels, a charge storage structure, a plurality of gate electrodes, a first semiconductor structure, and a protection layer pattern. The substrate includes a first region and a second region. The plurality of channels is disposed in the first region. The plurality of channels extends in a first direction substantially perpendicular to a top surface of the substrate. The charge storage structure is disposed on a sidewall of each channel. The plurality of gate electrodes is arranged on a sidewall of the charge storage structure and is spaced apart from each other in the first direction. The first semiconductor structure is disposed in the second region. The protection layer pattern covers the first semiconductor structure. The protection layer pattern has a thickness substantially similar to a thickness of a lowermost gate electrode.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate including a first region and a second region;
a plurality of channels in the first region, the plurality of channels extending in a first direction that is substantially perpendicular to a top surface of the substrate;
a charge storage structure on a sidewall of ones of the plurality of channels;
a plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction;
a first semiconductor structure in the second region; and
a protection layer pattern covering the first semiconductor structure, the protection layer pattern having a thickness that is substantially similar to a thickness of a lowermost one of the gate electrodes.

2. The vertical memory device of claim 1 , wherein the gate electrodes extend in a second direction that is substantially parallel to the top surface of the substrate, the lowermost gate electrode and the protection layer pattern are spaced apart from each other in the second direction, and the first semiconductor structure is spaced apart from the first region in the second direction.

3. The vertical memory device of claim 2 , further comprising a plurality of remaining sacrificial layer patterns that are at a same level as the plurality of gate electrodes respectively,
wherein a length of each remaining sacrificial layer pattern in a third direction that is substantially perpendicular to the first direction and the second direction gradually decreases, as a level of each remaining sacrificial layer pattern gets higher.

4. The vertical memory device of claim 3 , further comprising a second semiconductor structure in the second region and that is spaced apart from the first region in the third direction,
wherein a lowermost one of the remaining sacrificial layer patterns covers the second semiconductor structure.

5. The vertical memory device of claim 3 , wherein a thickness of the lowermost one of the remaining sacrificial layer patterns is substantially identical to the thickness of the protection layer pattern.

6. The vertical memory device of claim 3 , wherein the lowermost one of the remaining sacrificial layer patterns and the protection layer pattern include a same material.

7. The vertical memory device of claim 3 , further comprising a second semiconductor structure in the second region and that is spaced apart from the first region in the third direction,
wherein the protection layer pattern substantially covers the second semiconductor structure.

8. The vertical memory device of claim 7 , wherein the remaining sacrificial layer pattern and the protection layer pattern are spaced apart from each other in the third direction.

9. The vertical memory device of claim 3 , further comprising an insulation layer pattern between adjacent ones of the gate electrodes,
wherein the adjacent ones of the gate electrodes are spaced apart from each other in the third direction.

10. The vertical memory device of claim 9 , wherein a length of the insulation layer pattern in the second direction is greater than a length of the lowermost one of the gate electrodes in the second direction.

11. A method of manufacturing a vertical memory device, the method comprising:
forming a first semiconductor structure on a substrate including a first region and a second region, the first semiconductor structure being in the second region;
forming a plurality of sacrificial layers and a plurality of insulating interlayers on the substrate alternately and repeatedly;
partially removing the sacrificial layers and the insulating interlayers to form a mold structure in the first region and the second region and a protection layer pattern in the second region simultaneously, the protection layer pattern covering the first semiconductor structure;
forming a plurality of holes through the sacrificial layers and the insulating interlayers to expose a top surface of the substrate in the first region;
forming a charge storage structure and a channel filling each of the holes;
partially removing the sacrificial layers to form a plurality of gaps exposing a sidewall of each charge storage structure; and
forming a gate electrode to fill each of the gaps.

12. The method of manufacturing a vertical memory device of claim 11 , after forming the charge storage structure and the channel, further comprising partially removing the insulating interlayers and the sacrificial layers to form an opening extending in a second direction that is substantially parallel to a top surface of the substrate.

13. The method of manufacturing a vertical memory device of claim 12 , wherein partially removing the sacrificial layers includes forming remaining sacrificial layer patterns in the second region, and
wherein a lowermost one of the remaining sacrificial layer patterns and the protection layer pattern are spaced apart from each other in the second direction.

14. The method of manufacturing a vertical memory device of claim 13 , before forming a plurality of sacrificial layers and a plurality of insulating interlayers, further comprising forming a second semiconductor structure in the second region on the substrate,
wherein the first semiconductor structure is spaced apart from the first region in the second direction, the second semiconductor structure is spaced apart from the first region in a third direction that is substantially perpendicular to the first direction and the second direction, and
wherein the lowermost one of the remaining sacrificial layer patterns substantially covers the second semiconductor device.

15. The method of manufacturing a vertical memory device of claim 13 , before forming a plurality of sacrificial layers and a plurality of insulating interlayers, further comprising forming a second semiconductor device in the second region on the substrate,
wherein the first semiconductor device is spaced apart from the first region in the second direction, the second semiconductor device is spaced apart from the first region in a third direction that is substantially perpendicular to the first direction and the second direction, and
wherein the protection layer pattern substantially covers the second semiconductor device.

16. A vertical memory device, comprising:
a substrate including a first region, a second region and a third region;
a first semiconductor structure in the second region;
a second semiconductor structure in the third region;
a charge storage structure on a sidewall of ones of a plurality of channels in the first region;
a plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in a first direction that is substantially perpendicular to a top surface of the substrate;
a plurality of remaining sacrificial layer patterns that are at a same level as the plurality of gate electrodes, respectively, wherein a lowermost one of the plurality of remaining sacrificial layer patterns substantially covers the second semiconductor; and
a protection layer pattern substantially covering the first semiconductor structure, the protection layer pattern having a thickness that is substantially similar to a thickness of a lowermost gate electrode.

17. The vertical memory device of claim 16 , wherein a length of each of the remaining sacrificial layer patterns in a third direction that is substantially perpendicular to the first direction and the second direction gradually decreases, as a level of each of the remaining sacrificial layer pattern gets higher.

Assignees

• Jung Won-Seok
• Kang Chang-Seok
• Lee Min-Yong
• Jin Sang-Woo
• Samsung Electronics Co Ltd

Inventors

• Jung Won-Seok
• Kang Chang-Seok
• Lee Min-Yong
• Jin Sang-Woo

Classifications

• H01L27/11575

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B51/00

  Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title