MOSFET with ultra low drain leakage

US9536945B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9536945-B1
Application numberUS-201514814142-A
CountryUS
Kind codeB1
Filing dateJul 30, 2015
Priority dateJul 30, 2015
Publication dateJan 3, 2017
Grant dateJan 3, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device, comprising: a monocrystalline substrate configured to form a channel region between two recesses in the substrate; a gate conductor formed on a passivation layer over the channel region; dielectric pads formed in a bottom of the recesses and configured to prevent leakage to the substrate; and source and drain regions formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region. 2. The semiconductor device as recited in claim 1 , wherein the n-type material includes ZnO. 3. The semiconductor device as recited in claim 2 , wherein the ZnO is Al-doped. 4. The semiconductor device as recited in claim 1 , wherein the source and drain regions extend over vertical sides of the dielectric pads. 5. The semiconductor device as recited in claim 1 , wherein the source and drain regions extend above a surface of the substrate. 6. The semiconductor device as recited in claim 1 , wherein the n-type material includes an amorphous phase. 7. The semiconductor device as recited in claim 1 , wherein the substrate includes a III-V materials and the source and drain regions include a II-VI material. 8. The semiconductor device as recited in claim 1 , wherein the source and drain regions extend below the passivation layer on sides of the recesses. 9. A semiconductor device, comprising: a III-V monocrystalline substrate having a passivation layer formed thereon, the substrate being configured to form a channel region between two recesses in the substrate, the recesses forming undercut regions in the substrate below the passivation layer; a gate conductor formed on the passivation layer over the channel region; dielectric pads formed in a bottom of the recesses between the undercut regions, the undercut regions being free from dielectric material of the dielectric pads, the dielectric pads being configured to prevent leakage to the substrate; and source and drain regions formed from ZnO deposited in the recesses over the dielectric pads, the source and drain regions making contact with the channel region. 10. The semiconductor device as recited in claim 9 , wherein the ZnO is Al-doped. 11. The semiconductor device as recited in claim 9 , wherein the source and drain regions extend over vertical sides of the dielectric pads. 12. The semiconductor device as recited in claim 9 , wherein the source and drain regions extend above a surface of the substrate. 13. The semiconductor device as recited in claim 9 , wherein the ZnO includes an amorphous phase. 14. The semiconductor device as recited in claim 9 , wherein the source and drain regions extend below the passivation layer in the undercut regions.

Assignees

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Classifications

  • N-type · CPC title

  • characterised by the sectional shape, e.g. T or inverted-T · CPC title

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • Oxides · CPC title

  • the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title

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What does patent US9536945B1 cover?
A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D62/151. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).