Halo region formation by epitaxial growth

Patent metadata

Field	Value
Publication number	US-9034741-B2
Application number	US-201313906644-A
Country	US
Kind code	B2
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.

First claim

We claim:

1. A method of forming a semiconductor device comprising the steps of:
forming a source recess and a drain recess in a semiconductor substrate on opposing sides of a gate positioned above the semiconductor substrate;
forming an epitaxial halo region at the bottom of the source and drain recesses lower than a channel region, wherein the epitaxial halo region comprises growing a sacrificial layer including a silicon-germanium or carbon-doped silicon material with the corresponding p-type or n-type dopant;
etching the source and drain recesses in the semiconductor substrate to form sigma-shaped source and drain recesses, wherein a portion of the epitaxial halo region remains on opposing lower sides of the sigma-shaped source and drain recesses;
epitaxially growing an embedded halo region along a perimeter of each of the sigma-shaped source and drain recesses;
removing a bottom area of the embedded halo region along the perimeter of both the sigma-shaped source and drain recesses; and
epitaxially growing a stressor material to fill the sigma-shaped source and drain recesses, wherein the filled sigma-shaped source and drain recesses form source and drain regions for conducting current through the channel.

2. The method of claim 1 , wherein epitaxially growing the stressor material comprises the step of epitaxially growing a silicon-germanium or carbon-doped silicon material including a p-type or n-type dopant.

3. The method of claim 1 , wherein the epitaxial halo region and the embedded halo region are grown with in-situ dopants, including boron, phosphorous, or arsenic.

4. The method of claim 1 , wherein the bottom area of the embedded halo region is removed by a reactive-ion etching technique to create a butting contact area.

5. The method of claim 1 , wherein the stressor material comprises opposite doping polarity relative to the epitaxial halo region and the embedded halo region.

6. The method of claim 1 , wherein the embedded halo region comprises a similar lattice constant as the semiconductor substrate.

7. The method of claim 1 , wherein the stressor material comprises a different lattice constant as the semiconductor substrate.

8. The method of claim 1 , wherein the epitaxial halo region is grown before the step of forming the sigma-shaped source and drain recesses.

9. The method of claim 1 , wherein the step of forming the gate includes:
forming a dummy poly gate; and
replacing the dummy poly gate with a metal high-k dielectric gate structure.

10. The method of claim 9 , wherein the step of forming a dummy poly gate occurs before the step of forming source and drain recesses, and the step of replacing the dummy poly gate occurs after the step of epitaxially growing the stressor material.

11. A method of forming a semiconductor device comprising the steps of:
forming a source recess and a drain recess in a semiconductor substrate on opposing sides of a gate positioned above the semiconductor substrate;
forming an epitaxial halo region at the bottom of the source and drain recesses lower than a channel region;
etching the source and drain recesses in the semiconductor substrate to form sigma-shaped source and drain recesses, a portion of the epitaxial halo region remains on opposing lower sides of the sigma-shaped source and drain recesses, wherein the epitaxial halo region is grown before the step of forming the sigma-shaped source and drain recesses;
epitaxially growing an embedded halo region along a perimeter of each of the sigma-shaped source and drain recesses;
removing a bottom area of the embedded halo region along the perimeter of both the sigma-shaped source and drain recesses; and
epitaxially growing a stressor material to fill the sigma-shaped source and drain recesses, wherein the filled sigma-shaped source and drain recesses form source and drain regions for conducting current through the channel.

12. The method of claim 11 , wherein epitaxially growing the stressor material comprises the step of epitaxially growing a silicon-germanium or carbon-doped silicon material including a p-type or n-type dopant.

13. The method of claim 11 , wherein the bottom area of the embedded halo region is removed by a reactive-ion etching technique to create a butting contact area.

14. The method of claim 11 , wherein the stressor material comprises opposite doping polarity relative to the epitaxial halo region and the embedded halo region.

15. The method of claim 11 , wherein the embedded halo region comprises a similar lattice constant as the semiconductor substrate.

16. The method of claim 11 , wherein the stressor material comprises a different lattice constant as the semiconductor substrate.

17. A method of forming a semiconductor device comprising the steps of:
forming a dummy poly gate;
forming a source recess and a drain recess in a semiconductor substrate on opposing sides of the dummy poly gate positioned above the semiconductor substrate;
epitaxially growing an embedded halo region along a perimeter of each of the source and drain recesses;
removing a bottom area of the embedded halo region along the perimeter of both the source and drain recesses; and
epitaxially growing a stressor material to fill the source and drain recesses, wherein the filled source and drain recesses form source and drain regions for conducting current through a channel; and
replacing the dummy poly gate with a metal high-k dielectric gate structure, wherein the step of forming a dummy poly gate occurs before the step of forming source and drain recesses, and the step of replacing the dummy poly gate occurs after the step of epitaxially growing the stressor material.

18. The method of claim 17 , wherein the source and drain recesses are sigma-shaped.

19. The method of claim 17 further comprising
forming an epitaxial halo region at the bottom of the source and drain recesses lower than the channel region.

20. The method of claim 19 , wherein the epitaxial halo region comprises growing a sacrificial layer including a silicon-germanium or carbon-doped silicon material with the corresponding p-type or n-type dopant.

Assignees

• IBM

Inventors

• Adam Thomas N
• Fogel Keith E
• Holt Judson R
• Pranatharthiharan Balasubramanian
• Reznicek Alexander

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D30/0218

  having pocket halo regions selectively formed at the sides of the gates · CPC title

• H10D30/797 Primary

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/159

  Shapes · CPC title