Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric

Patent metadata

Field	Value
Publication number	US-9337264-B2
Application number	US-201514664435-A
Country	US
Kind code	B2
Filing date	Mar 20, 2015
Priority date	Jul 6, 2010
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.

First claim

What is claimed is:

1. A field-effect transistor (FET) device, comprising:
a silicon-on-insulator (SOI) wafer having a SOI layer over a buried oxide (BOX);
nanowires and pads patterned in the SOI layer with the pads attached at opposite ends of the nanowires in a ladder-like configuration, wherein the BOX is recessed under the nanowires;
at least one gate over the recessed BOX and surrounding a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the at least one gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one gate comprise source and drain regions of the FET;
at least one partial dummy gate present on the BOX below the nanowires and the at least one gate, wherein the at least one gate is present on top of, and has a same footprint as, the at least one partial dummy gate;
a CMP stop layer over the source and drain regions; and
a planarized dielectric film over the CMP stop layer.

2. The FET device of claim 1 , further comprising:
a gate dielectric around the nanowires in the channel region.

3. The FET device of claim 1 , further comprising:
spacers on each sidewall of the at least one gate.

4. The FET device of claim 3 , wherein the spacers comprise nitride spacers.

5. The FET device of claim 1 , further comprising:
epitaxial silicon, germanium or silicon germanium over the source and drain regions.

6. The FET device of claim 1 , wherein the source and drain regions are doped.

7. The FET device of claim 1 , further comprising:
a metal silicide, germanide or germanosilicide over the source and drain regions.

8. The FET device of claim 1 , further comprising:
a second CMP stop layer over the planarized dielectric film; and
contacts to the source and drain regions that extend through the CMP stop layer, the second CMP stop layer and the planarized dielectric film.

9. The FET device of claim 1 , comprising dual gates.

10. The FET device of claim 1 , wherein the at least one partial dummy gate comprises hydrogen silsesquioxane and the at least one gate comprises at least one conductor material.

11. A FET device, comprising:
a SOT wafer having a SOT layer over a BOX;
a stack of alternating layers of silicon germanium and silicon on the SOT layer;
a plurality of nanowires and pads patterned in the SOT layer and in each of the silicon layers in the stack, wherein the BOX is recessed under the nanowires;
at least one gate over the recessed BOX and surrounding a portion of each of the nanowires, wherein the portions of the nanowires surrounded by the at least one gate comprise a channel region of the FET and wherein the pads and portions of the nanowires extending out from the at least one gate comprise source and drain regions of the FET;
at least one partial dummy gate present on the BOX below the nanowires and the at least one gate, wherein the at least one gate is present on top of, and has a same footprint as, the at least one partial dummy gate;
a CMP stop layer over the source and drain regions; and
a planarized dielectric film over the CMP stop layer.

12. The FET device of claim 11 , wherein the at least one gate has substantially straight sidewalls.

13. The FET device of claim 11 , wherein the at least one gate underlaps the pads.

14. The FET device of claim 11 , further comprising:
a gate dielectric around the nanowires in the channel region.

15. The FET device of claim 11 , further comprising:
spacers on each sidewall of the at least one gate.

16. The FET device of claim 15 , wherein the spacers comprise nitride spacers.

17. The FET device of claim 11 , further comprising:
epitaxial silicon, germanium or silicon germanium over the source and drain regions.

18. The FET device of claim 11 , wherein the source and drain regions are doped.

19. The FET device of claim 11 , further comprising:
a metal silicide, germanide or germanosilicide over the source and drain regions.

Assignees

• Globalfoundries Inc

Inventors

• Bangsaruntip Sarunya
• Cohen Guy
• Guillorn Michael A

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title