Semiconductor Structure Having Integrated Snubber Resistance and Related Method

Patent metadata

Field	Value
Publication number	US-2016104773-A1
Application number	US-201514870394-A
Country	US
Kind code	A1
Filing date	Sep 30, 2015
Priority date	Oct 9, 2014
Publication date	Apr 14, 2016
Grant date	—

Abstract

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

First claim

1 . A semiconductor structure comprising:
a source trench in a drift region, said source trench having a source trench dielectric liner and a source trench conductive filler surrounded by said source trench dielectric liner; a source region in a body region over said drift region; a patterned source trench dielectric cap forming an insulated portion and an exposed portion of said source trench conductive filler; a source contact layer coupling said source region to said exposed portion of said source trench conductive filler, said insulated portion of said source trench conductive filler increasing resistance between said source contact layer and said source trench conductive filler under said patterned source trench dielectric cap.

2 . The semiconductor structure of claim 1 wherein said insulated portion of said source trench conductive filler is configured to increase damping of output signals generated by said semiconductor structure during electrical operation.

3 . The semiconductor structure of claim 1 wherein said insulated portion of said source trench conductive filler and a capacitance under said insulated portion of said source trench conductive filler are configured to increase damping of output signals generated by said semiconductor structure during electrical operation.

4 . The semiconductor structure of claim 1 wherein said source trench includes at least two parallel portions and a curved portion connecting said at least two parallel portions.

5 . The semiconductor structure of claim 1 wherein said source trench conductive filler includes polysilicon.

6 . The semiconductor structure of claim 1 further comprising a gate trench adjacent to said source region and extending through said body region into said drift region.

7 . The semiconductor structure of claim 6 further comprising a gate trench dielectric cap over said gate trench.

8 . The semiconductor structure of claim 1 wherein said source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

9 . The semiconductor structure of claim 8 wherein said plurality of parallel portions have substantially uniform spacing.

10 . The semiconductor structure of claim 8 further comprising a termination trench enclosing said serpentine source trench.

11 . A method of forming a semiconductor structure, the method comprising:
forming a source trench in a drift region; forming a source trench dielectric liner and a source trench conductive filler surrounded by said source trench dielectric liner; forming a source region in a body region over said drift region; forming a patterned source trench dielectric cap, said patterned source trench dielectric cap forming an insulated portion and an exposed portion of said source trench conductive filler; forming a source contact layer coupling said source region to said exposed portion of said source trench conductive filler, said insulated portion of said source trench conductive filler increasing resistance between said source contact layer and said source trench conductive filler under said patterned source trench dielectric cap.

12 . The method of claim 11 wherein said insulated portion of said source trench conductive filler is configured to increase damping of output signals generated by said semiconductor structure during electrical operation.

13 . The method of claim 11 wherein said insulated portion of said source trench conductive filler and a capacitance under said insulated portion of said source trench conductive filler are configured to increase damping of output signals generated by said semiconductor structure during electrical operation.

14 . The method of claim 11 wherein said source trench includes at least two parallel portions and a curved portion connecting said at least two parallel portions.

15 . The method of claim 11 wherein said source trench conductive filler includes polysilicon.

16 . The method of claim 11 further comprising forming a gate trench adjacent to said source region and extending through said body region into said drift region.

17 . The method of claim 16 further comprising forming a gate trench dielectric cap over said gate trench.

18 . The method of claim 11 wherein said source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

19 . The method of claim 18 wherein said plurality of parallel portions have substantially uniform spacing.

20 . The method of claim 18 wherein said serpentine source trench is enclosed by a termination trench.

Assignees

• Int Rectifier Corp

Inventors

• Kelkar Kapil
• Henson Timothy D
• Ma Ling
• Bigglestone Mary
• Amali Adam
• Burke Hugo
• Haase Robert

Classifications

• H10W42/20

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D64/115

  Resistive field plates, e.g. semi-insulating field plates · CPC title

• H10D62/155

  Shapes  (cell layout of DMOS H10D62/127) · CPC title