Circuit arrangement, a method for forming a circuit arrangement, and method for integrity checking

Patent metadata

Field	Value
Publication number	US-9536086-B2
Application number	US-201213401885-A
Country	US
Kind code	B2
Filing date	Feb 22, 2012
Priority date	Feb 22, 2012
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A circuit arrangement is provided, the circuit arrangement including a processor; a memory circuit connected to the processor, wherein the processor is configured to access the memory circuit; a blocking circuit configured to generate one or more random wait state signals which prevent the processor from accessing the memory circuit; and an integrity checking circuit configured to check the memory circuit during a wait state period of the one or more random wait state signals.

First claim

What is claimed is:

1. A circuit arrangement, comprising:
a processor, wherein the processor is configured to perform at least one cryptographic algorithm and to generate an associated signal related to execution properties of the at least one cryptographic algorithm;
a memory circuit connected to the processor, wherein the processor is configured to access the memory circuit;
a blocking circuit configured to generate one or more randomly generated wait state signals which prevent the processor from accessing the memory circuit,
wherein the blocking circuit is configured to generate the one or more randomly generated wait state signals during execution of instructions by the processor, which halt the execution of instructions by the processor and which alters the associated signal; and
an integrity checking circuit configured to access the memory circuit during a wait state period of the one or more random wait state signals,
wherein the integrity checking circuit is configured to perform an integrity check on memory data in the memory circuit during a randomly generated wait state period during which the processor halts execution of instructions.

2. The circuit arrangement according to claim 1 ,
wherein the blocking circuit is configured to generate one or more randomly generated wait state signals which triggers the integrity checking circuit to access the memory circuit during a wait state period wherein the processor is prevented from accessing the memory circuit.

3. The circuit arrangement of claim 2 , wherein the one or more randomly generated wait state signals prevent unwanted side-channel attacks.

4. The circuit arrangement according to claim 1 , wherein the processor is configured to perform at least one cryptographic algorithm from the following group of cryptographic algorithms, the group consisting of: authentication algorithms, ciphering algorithms; and hash-function algorithms.

5. The circuit arrangement according to claim 1 , wherein the processor is configured to perform at least one ciphering algorithm from the following group of ciphering algorithms, the group consisting of: symmetric ciphering algorithm; and asymmetric ciphering algorithm.

6. The circuit arrangement according to claim 5 ,
wherein the processor is configured to perform a symmetric block-ciphering algorithm.

7. The circuit arrangement according to claim 1 , wherein the processor is configured to perform a block-ciphering algorithm.

8. The circuit arrangement according to claim 1 , wherein the associated signal comprises at least one type of from the following group of types of information, the group consisting of: timing information, power consumption information, electromagnetic radiation information.

9. The circuit arrangement according to claim 1 , wherein the integrity checking circuit is configured to perform an integrity check on a predetermined set of memory data in the memory circuit.

10. The circuit arrangement of claim 9 , wherein in response to the integrity checking circuit detecting a change in the memory content, the circuit arrangement is configured to prevent processor access to at least a portion of the memory circuit.

11. The circuit arrangement according to claim 1 , further comprising
a read-only memory circuit configured to store one or more integrity checking instructions.

12. The circuit arrangement according to claim 1 ,
wherein the integrity checking circuit is configured to receive one or more integrity checking instructions comprising a set of memory data and a location of the memory data to be checked.

13. The circuit arrangement according to claim 1 ,
wherein the integrity checking circuit is configured to perform an algorithm to determine a state of memory data in the memory circuit.

14. The circuit arrangement according to claim 13 ,
wherein the integrity checking circuit is configured to perform at least one algorithm from the following group of algorithms, the group consisting of: ciphering algorithm; and hash-function algorithm.

15. The circuit arrangement according to claim 14 ,
wherein the integrity checking circuit is configured to perform a symmetric block-ciphering algorithm.

16. The circuit arrangement according to claim 13 ,
wherein the integrity checking circuit is configured to perform a block-ciphering algorithm.

17. The circuit arrangement according to claim 13 ,
wherein the integrity checking circuit is configured to perform at least one ciphering algorithm from the following group of ciphering algorithms, the group consisting of: secret key ciphering algorithm; and public key ciphering algorithm.

18. The circuit arrangement according to claim 13 ,
wherein the integrity checking circuit is configured to determine whether or not the state of memory data in the memory circuit matches a reference state value.

19. The circuit arrangement according to claim 13 ,
wherein the integrity checking circuit is further configured to output a signal indicating that the integrity of the memory data is maintained wherein the state of the memory data in the memory circuit resulting from the integrity check matches a reference state value; and to output a signal indicating that the integrity of the memory data is not maintained wherein the state of the memory data in the memory circuit resulting from the integrity check does not match a reference state value.

20. The circuit arrangement according to claim 19 ,
wherein the processor is configured to access the memory circuit wherein the output signal indicates that the integrity of the memory data is maintained; and
wherein the processor is configured to be prevented from access to the memory circuit wherein the output signal indicates that the integrity of the memory data is not maintained.

21. The circuit arrangement according to claim 1 , further comprising
a non-volatile memory circuit configured to store at least one of a reference state value and a seed value.

22. The circuit arrangement according to claim 1 , further comprising
a controller circuit configured to perform at least one task from the following group of tasks when it is determined by the integrity check circuit that a state of the memory data in the memory circuit does not match a reference state value,
the at least one task comprising at least one from the following group of actions, the group consisting of: halting the processor, removing power from the processor, resetting the memory circuit, stopping a processor clock.

23. The circuit arrangement according to claim 1 ,
wherein the memory circuit comprises at least one memory circuit from the following group of memory circuits, the group of memory circuits consisting of: a non-volatile memory, a random access memory, a read only memory, and a flash memory.

24. The circuit arrangement according to claim 1 ,
wherein the memory circuit comprises at least one memory circuit from the following group of memory circuits, the group of memory circuits consisting of: a magnetoresistive random access memory, a conductive bridge random access memory, a phase change element random access memory, a programmable read only memory, an erasable programmable read only memory, an electrically erasable programmable read only memory, a static random access memory.

25. The circuit arrangement according to claim 1 , further comprising
a direct memory access controller configured to transfer memory data from the memor

Assignees

• Furtner Wolfgang
• Infineon Technologies Austria Ag

Inventors

• Furtner Wolfgang

Classifications

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• Y10T29/49004

  including measuring or testing of device or component part · CPC title

• G06F21/558 Primary

  Physics · mapped topic

• G06F21/755 Primary

  with measures against power attack · CPC title