Method and apparatus for monitoring performance for secure chip operation

Patent metadata

Field	Value
Publication number	US-9310862-B2
Application number	US-201414282451-A
Country	US
Kind code	B2
Filing date	May 20, 2014
Priority date	May 20, 2013
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A method and apparatus is provided for monitoring performance of an processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor. In one example, the method and apparatus compares a measured value of an operating parameter (i.e., a temperature, supply voltage or clock signal) to predefined limits to identify an out of limits measured value. If an out of limits measured value is detected during a normal operating mode, the processor enters a reset mode, and if an out of limits measured value is detected during power up or reset, the processor in retained a reset mode.

First claim

What is claimed is:

1. A method of monitoring performance of a processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor, comprising:
during a normal operating mode and at least one of a power up and a reset mode, comparing a measured value of an operating parameter to a predefined set of high and low limits for the measured value to identify an out of limits measured value; and
if an out of limits measured value is detected during the normal operating mode, causing the processor to enter a reset mode, and if an out of limits measured value is detected during the at least one of a power up and a reset mode, retaining the processor in a reset mode;
wherein comparing a measured value comprises providing a plurality of minimum and maximum input signals from a digital circuit to an analog circuit, the plurality of minimum and maximum input signals corresponding to the predefined set of high and low limits, and receiving at the digital circuit a plurality of minimum and maximum output signals from the analog circuit, the plurality of minimum and maximum output signals corresponding to results of comparisons of the operating parameter to values determined by the minimum and maximum input signals.

2. The method of claim 1 , wherein the measured value is compared to a set of coarse high and low limits during the at least one of a power up and a reset mode, and is compared to a set of calibrated high and low limits during the normal operating mode.

3. The method of claim 1 , wherein the operating parameter is one of a temperature, a supply voltage, and a clock signal.

4. A method of monitoring performance of a processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor, comprising:
during a normal operating mode and at least one of a power up and a reset mode, comparing a measured value of an operating temperature of the processor to a predefined set of high and low limits for the measured value to identify an out of limits measured value; and
if an out of limits measured value is detected during the normal operating mode, causing the processor to enter a reset mode, and if an out of limits measured value is detected during the at least one of a power up and a reset mode, retaining the processor in a reset mode;
wherein comparing a measured value comprises generating a first voltage across a first resistor being proportional to the operating temperature, generating a second voltage across a second resistor being proportional to the operating temperature, generating a temperature-independent first reference voltage as a function of a minimum limit input value, generating a temperature-independent second reference voltage as a function of a maximum limit input value, comparing the first voltage to the first reference voltage to determine if the first voltage is below the low limit, and comparing the second voltage to the second reference voltage to determine if the second voltage is above the high limit.

5. The method of claim 4 , wherein during power up and during reset mode, the maximum limit input value corresponds to a predefined coarse high limit and the minimum limit input value corresponds to a predefined coarse low limit, and during the normal operating mode, the maximum limit input value corresponds to a predefined calibrated high limit and the minimum limit input value corresponds to a predefined calibrated low limit.

6. A method of monitoring performance of a processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor, comprising:
during a normal operating mode and at least one of a power up and a reset mode, comparing a measured value of one of a plurality of supply voltages to the processor to a predefined set of high and low limits for the measured value to identify an out of limits measured value; and
if an out of limits measured value is detected during the normal operating mode, causing the processor to enter a reset mode, and if an out of limits measured value is detected during the at least one of a power up and a reset mode, retaining the processor in a reset mode;
wherein comparing a measured value comprises dividing the one supply voltage in a first divider circuit that is a function of a maximum limit input value to produce a first voltage, dividing the one supply voltage in a second divider circuit that is a function of a minimum limit input value to produce a second voltage, generating a temperature-independent reference voltage, comparing the first voltage to the reference voltage to determine if the first voltage is above the high limit, and comparing the second voltage to the reference voltage to determine if the second voltage is below the low limit.

7. The method of claim 6 , wherein when the one supply voltage is identified as presenting a tampering security risk, the maximum limit input value corresponds to a predefined coarse high limit and the minimum limit input value corresponds to a predefined coarse low limit, and when the one supply voltage is identified as not presenting a tampering security risk, the maximum limit input value corresponds to a predefined calibrated high limit and the minimum limit input value corresponds to a predefined calibrated low limit.

8. A method of monitoring performance of a processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor, comprising:
during a normal operating mode and at least one of a power up and a reset mode, comparing a measured value of a reference clock signal to a predefined set of high and low limits for the measured value to identify an out of limits measured value; and
if an out of limits measured value is detected during the normal operating mode, causing the processor to enter a reset mode, and if an out of limits measured value is detected during the at least one of a power up and a reset mode, retaining the processor in a reset mode;
wherein comparing a measured value comprises counting oscillations of a ring oscillator between rising edges of the reference clock signal to produce a period signal, counting oscillations of the ring oscillator between sequential rising and falling edges of the reference clock signal to produce a low time signal, comparing the period signal to predefined high and low limits to determine if the period signal is out of limits, and comparing the low time signal to predefined high and low limits to determine if the low time signal is out of limits.

9. The method of claim 8 , wherein during power up and during reset mode, the predefined high and low limits are coarse limits, and during the normal operating mode, the predefined high and low limits are calibrated limits.

10. The method of claim 8 , wherein comparing a measured value comprises counting oscillations of the ring oscillator after a rising edge of the reference clock signal and generating an overflow signal indicating that the reference clock has stopped if the counted oscillations exceeds a predefined limit.

11. An apparatus for monitoring performance of a processor to detect tampering and place the processor in a safe operating state that prevents unauthorized access to contents of the processor, comprising:
a circuit that compares, during a normal operating mode and at least one of a power up and a reset mode, a first measured value being proportional to an operating temperature of the processor to a predefined set of high and low limits for the measured value to identify an out of limits measured value;
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Assignees

• Advanced Micro Devices Inc
• Advanced Micro Devices Inc

Inventors

• Cabler Carlin Dru
• Nussbaum Sebastien
• Disanza Leonard
• Nix Michael A
• Kosonocky Stephen
• Hirsch Thomas

Classifications

• H04L9/002

  Countermeasures against attacks on cryptographic mechanisms (network architectures or network communication protocols for protection against malicious traffic H04L63/1441) · CPC title

• G06F21/57

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F21/558

  Physics · mapped topic

• G06F21/71

  to assure secure computing or processing of information · CPC title