Method of executing, by a microprocessor, a polymorphic binary code of a predetermined function

Patent metadata

Field	Value
Publication number	US-9489315-B2
Application number	US-201414504003-A
Country	US
Kind code	B2
Filing date	Oct 1, 2014
Priority date	Oct 1, 2013
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

Executing polymorphic binary code of a predetermined function includes acquiring polymorphic binary code of the function, the code having instruction blocks and control instructions. One block acquires a random number; the other defines a specific generator that generates target instructions to execute the function. The control instructions place the target instructions in memory. Each instruction has an opcode that codes a nature of an operation to be executed, and operands that define parameters of the operation. The generator incorporates coding variants of the function and selection instructions. Each variant generates instructions that perform the function. These instructions differ from each other and enable choosing a variant, based on the random number, to generate the target instructions. The choice is made only between different coding variants of the predetermined function.

First claim

Having described the invention, and a preferred embodiment thereof, what is claimed as new and secured by Letters Patent is:

1. A method of executing, by a microprocessor, polymorphic binary code of a predetermined function, said method comprising providing a microprocessor, wherein said microprocessor comprises one or more arithmetic and logic units, wherein said microprocessor comprises a memory configured to store instructions to be executed by said one or more arithmetic and logic units in a particular order, acquiring polymorphic binary code of a predetermined function, wherein said polymorphic binary code comprises a first block of instructions, wherein said polymorphic binary code comprises a second block of instructions, wherein said first block of instructions comprises instructions that, when executed by said microprocessor, result in acquisition of a random number, wherein said second block of instructions comprises instructions that, when executed by said microprocessor, define a specific generator, wherein said specific generator, when executed by said microprocessor, generates a set of target instructions, wherein said set of target instructions, when executed by said microprocessor, carries out said predetermined function, wherein said polymorphic binary code further comprises control instructions, wherein said control instructions are configured for placing said set of target instructions, which are generated by said specific generator, into memory, wherein placement of said set of target instructions generated by said specific generator into memory occurs in response to execution of said control instructions by said microprocessor, wherein said specific generator incorporates a plurality of coding variants of said predetermined function and selection instructions, wherein each coding variant of said plurality of coding variants generates, when executed by said microprocessor, a specific set of instructions that perform said predetermined function, wherein each instruction of said specific set of instructions comprises an opcode and one or more operands, wherein said opcode codes a nature of an operation to be executed, wherein said one or more operands define one or more values of parameters of said operation to be executed, wherein said specific sets of instructions are distinguished from one another by difference in at least one instruction opcode, one operand, a literal value, and a number of instructions, wherein, during execution of said specific generator by said microprocessor, said selection instructions make it possible to choose, from said plurality of available coding variants, a coding variant to be executed to generate said set of target instructions, wherein said choice is a function of a random number, wherein said method further comprises acquiring a random number through execution by said microprocessor of said first block of instructions, choosing a coding variant to be executed through execution by said microprocessor of said selection instructions, wherein a choice of coding variant is made as a function of said acquired random number, generating, through execution by said microprocessor, of said specific generator, of said set of target instructions by executing said coding variant chosen as a function of said acquired random number, shifting in said memory of said microprocessor, through execution by said microprocessor of said control instructions, said set of target instructions generated for said microprocessor to execute said target instructions, and executing said set of target instructions by said microprocessor, and wherein said choice of said coding variant to be executed is systematically made only between different coding variants of said predetermined function.

2. The method of claim 1 , wherein said random number is pseudo-random.

3. The method of claim 1 , further comprising selecting said binary code to represent a cryptographic primitive.

4. A manufacture comprising a non-transitory computer-readable medium having encoded thereon polymorphic binary code of a predetermined function, said binary code being directly executable by a microprocessor that comprises one or more arithmetic and logic units, and a memory in which instructions are stored, wherein said instructions are to be executed by said one or more arithmetic and logic units in a particular order, wherein each instruction comprises an opcode and one or more operands, wherein said opcode codes a nature of an operation to be executed, wherein said one or more operands define one or more values of parameters of said operation to be executed, wherein said polymorphic binary code further comprises a first block of instructions, a second block of instructions, and control instructions, wherein said first block of instructions comprises instructions that, when executed by said microprocessor, acquiring a random number, wherein said second block of instructions comprise instructions for implementing a specific generator, wherein, when executed by said microprocessor, said specific generator generates a set of target instructions, wherein, when executed by said microprocessor, said set of target instructions performs said predetermined function, wherein, when executed by said microprocessor, said control instructions place said target instructions into said memory, wherein said specific generator comprises a plurality of coding variants of said predetermined function, wherein, when executed by said microprocessor, each coding variant generates a specific set of target instructions for performing said predetermined function, wherein said sets of instructions from said specific set of instructions are distinguished from one another by a difference in at least one of an instruction opcode, an operand, a literal value, and a number of instructions, wherein said instructions further comprise selection instructions that make it possible to choose from said plurality of available coding variants, as a function of said random number during execution of said specific generator by said microprocessor, and wherein said specific generator comprises selection instructions that make it possible to choose only coding variants of said predetermined function such that said specific generator has no selection instructions that make it possible to choose coding variants of a function other than said predetermined function.

5. The manufacture of claim 4 , wherein at least one of said coding variants to be executed comprises an operand whose value is a function of a random number such that said specific set of target instructions generated by execution of said coding variant varies as a function of said random number.

6. The manufacture of claim 5 , wherein said random number is a random number acquired by said first block.

7. The manufacture of claim 4 , wherein said control instructions are suitable for modifying, as a function of a random number, an order in said memory of at least two instructions of said set of target instructions generated by said specific generator.

8. The manufacture of claim 4 , wherein at least one coding variant comprises an instruction whose operand corresponds to an identifier of a memory register of said microprocessor, and wherein said binary code comprises instructions for modifying a value of said operand as a function of the same or of another random number so as to modify an assignment of registers of said microprocessor each time said random number is modified.

9. The manufacture of claim 4 , wherein said predetermined function is configured to process a datum having a value that is only known at upon execution of said predetermined function by said microprocessor, wherein said specific generator is configured for generating a set of specific instructi

Assignees

• Commissariat Á L'Energie Atomique Et Aux Énergies Alternatives
• Commissariat L Energie Atomique Et Aux Energies Alternatives

Inventors

• Courousse Damien

Classifications

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F21/558

  Physics · mapped topic