Countermeasure method for protecting stored data

US9483663B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9483663-B2
Application numberUS-84913010-A
CountryUS
Kind codeB2
Filing dateAug 3, 2010
Priority dateAug 5, 2009
Publication dateNov 1, 2016
Grant dateNov 1, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of read or write access by an electronic component of data, including generating a first secret key for a first data of an ordered list of data to access, and for each data of the list, following the first data, generating a distinct secret key by means of a deterministic function applied to a secret key generated for a previous data of the list, and the application of a cryptographic operation to each data to be read or to be written of the list, carried out by using the secret key generated for the data.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method, comprising: generating a first secret key for a first data of an ordered list of data read or to be written by an electronic device; for each data of the list, following the first data, generating a distinct secret key based on a deterministic function; applying a cryptographic operation to each data read or to be written of the list based on the secret key generated for the data, wherein the deterministic function is applied to a secret key generated for a previous data of the list and at least one of: the previous data; and a result of application of the cryptographic operation to the previous data; comparing a result of application of the cryptographic operation to a last data of the ordered list to a reference data; and selectively causing the electronic device to enter an error state based on the comparison, wherein the generation of a secret key for a data of the list is started by a particular instruction detected before the access to the data, during the execution of a program by the electronic device. 2. The method according to claim 1 wherein the deterministic function is a generation function of pseudo-random numbers. 3. The method according to claim 1 wherein when the comparison reveals a difference, the electronic device passes into the error state. 4. The method according to claim 1 wherein the generation of a secret key for a data of the list is started when an address of the data belongs to an ensemble of particular addresses. 5. The method according to claim 1 wherein if a secret key is not generated for an accessed data, the cryptographic operation applied to the accessed data uses a common secret key. 6. The method according to claim 1 wherein the first secret key is generated by applying the deterministic function to an initial value. 7. The method according to claim 1 , comprising two consecutive read accesses to a same storage address of data, carried out by using two distinct secret keys so that the cryptographic operation supplies two different data. 8. The method according to claim 1 , comprising two consecutive read accesses to two distinct data storage addresses, carried out by using two distinct secret keys such that the cryptographic operation supplies two identical data. 9. The method of claim 1 wherein the deterministic function is applied to the result of application of the cryptographic operation to the previous data. 10. An electronic device, comprising: a key generator configured to: generate a first secret key for a first data of an ordered list of data read or to be written by the electronic device; and for each data of the list, following the first data, generate a distinct secret key based on a deterministic function; a cryptographic unit coupled to the key generator and configured to apply a cryptographic operation to each data read or to be written of the list based on the secret key generated for the data, wherein the deterministic function is applied to a secret key generated for a previous data of the list and at least one of: the previous data; and a result of application of the cryptographic operation to the previous data; a comparator configured to: compare a result of application of the cryptographic operation to a last data of the ordered list to a reference data; and control a state of the electronic device based on the comparison, wherein the electronic device includes one or more processing devices configured to implement the key generator, the cryptographic unit and the comparator; a memory storing instructions; and a processor configured to execute the instructions, wherein the generation of a secret key for a data of the list is started by a particular instruction detected before the access to the data, during the execution of a program by the electronic device. 11. The electronic device of claim 10 wherein the deterministic function is a generation function of pseudo-random numbers. 12. The electronic device of claim 10 wherein the comparator is configured to generate a signal to cause the electronic device to enter an error state when the comparison reveals a difference. 13. The electronic device of claim 10 , further comprising an address decoder, wherein the key generator is configured to start generation of a secret key for a data of the list when the address decoder determines an address of the data belongs to an ensemble of particular addresses. 14. The electronic device of claim 10 wherein the key generator is configured to generate the first secret key by applying the deterministic function to an initial value. 15. The electronic device of claim 10 wherein the cryptographic unit is configured to perform two consecutive cryptographic operations on data associated with a single storage address, carried out by using two distinct secret keys, producing two different output data. 16. The electronic device of claim 10 wherein the cryptographic unit is configured to perform two consecutive cryptographic operations on data associated with two distinct data storage addresses, carried out by using two distinct secret keys, producing identical output data. 17. A system, comprising: a processor; a memory; a countermeasure device coupled between the processor and the memory, the countermeasure device comprising: a key generator configured to: generate a first secret key for a first data of an ordered list of data to be transferred between the processor and the memory; and for each data of the list, following the first data, generate a distinct secret key based on a deterministic function; and a cryptographic unit coupled to the key generator and configured to apply a cryptographic operation to each data of the list based on the secret key generated for the data, wherein the deterministic function is applied to a secret key generated for a previous data of the list and at least one of: the previous data; and a result of application of the cryptographic operation to the previous data; and an error detector configured to: compare a result of application of the cryptographic operation to a last data of the ordered list to a reference data; and control a state of the system based on the comparison, wherein the generation of a secret key for a data of the list is started by a particular instruction detected before the access to the data, during the execution of a program the processor. 18. The system of claim 17 wherein the error detector is configured to generate a signal to cause the electronic device to enter an error state when the comparison reveals a difference. 19. The system of claim 17 , further comprising an address decoder, wherein the key generator is configured to start generation of a secret key for a data of the list when the address decoder determines an address of the data belongs to an ensemble of particular addresses. 20. The system of claim 17 wherein the cryptographic unit is configured to perform two consecutive cryptographic operations on data associated with a single storage address, carried out by using two distinct secret keys, producing two different output data. 21. The system of claim 17 wherein the cryptographic unit is configured to perform two consecutive cryptographic operations on data associated with two distinct data storage addresses, carried out by using two distinct secret keys, producing identical output data. 22. The system of claim 17 wherein the deterministic function is applied to the result of

Assignees

Inventors

Classifications

  • Protecting access to data via a platform, e.g. using keys or access control rules · CPC title

  • G06F21/78Primary

    to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

  • for fault attacks · CPC title

  • File encryption · CPC title

  • Physics · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9483663B2 cover?
A method of read or write access by an electronic component of data, including generating a first secret key for a first data of an ordered list of data to access, and for each data of the list, following the first data, generating a distinct secret key by means of a deterministic function applied to a secret key generated for a previous data of the list, and the application of a cryptographic …
Who is the assignee on this patent?
Bancel Frédéric, Stmicroelectronics Rousset
What technology area does this patent fall under?
Primary CPC classification G06F21/78. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).