Semiconductor component and an operating method for a protective circuit against light attacks

Patent metadata

Field	Value
Publication number	US-9419623-B2
Application number	US-201414512686-A
Country	US
Kind code	B2
Filing date	Oct 13, 2014
Priority date	Apr 21, 2011
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

First claim

What is claimed is:

1. A semiconductor component, comprising:
a semiconductor substrate;
a doped well formed in the semiconductor substrate, the doped well having a well terminal;
a transistor structure formed in the semiconductor substrate, the transistor structure having a potential terminal and a parasitic thyristor partly arranged in the doped well; and
a resistor connecting the potential terminal and the well terminal,
wherein the parasitic thyristor is configured to initiate a latch-up or latch-up preliminary stage responsive to a light attack on the semiconductor component,
wherein data stored on the semiconductor component and/or a function of the semiconductor component is disturbed or destroyed in the latch-up or latch-up preliminary stage.

2. A semiconductor component according to claim 1 , wherein the resistor is operable such that that a light attack turns on the parasitic thyristor.

3. A semiconductor component according to claim 1 , wherein the resistor is arranged outside the doped well.

4. A semiconductor component according to claim 3 , wherein the resistor is a polysilicon resistor or a metal resistor.

5. A semiconductor component according to claim 1 , wherein the resistor is arranged outside the semiconductor substrate.

6. A semiconductor component according to claim 5 , wherein the resistor is a polysilicon resistor or a metal resistor.

7. A semiconductor component according to claim 1 , wherein the resistor is formed in the semiconductor substrate, in a doped well and/or in a diffusion region.

8. A semiconductor component according to claim 1 , wherein the resistor is an adjustable resistor and the semiconductor component is operable such that the sensitivity of the parasitic thyristor to light attacks is adjustable by an adjustment of the resistor.

9. A semiconductor component according to claim 1 , wherein the resistor is a regulable resistor and the semiconductor component is operable to regulate the resistor based on a physical variable measured in the semiconductor component.

10. A semiconductor component according to claim 1 , wherein the semiconductor component is a CMOS semiconductor component.

11. A semiconductor component according to claim 1 , wherein the semiconductor component comprises a plurality of transistor structures each having a parasitic thyristor.

12. A semiconductor component according to claim 11 , wherein the resistor is connected to the potential terminals of the plurality of transistor structures.

13. A semiconductor component according to claim 1 , wherein the doped well is an n-type well and the electrical potential present at the potential terminal is a positive supply voltage.

14. A semiconductor component according to claim 1 , wherein the semiconductor component comprises a logic circuit and the transistor structure is a part of the logic circuit.

15. A semiconductor component according to claim 1 , further comprising a current limiting circuit operable to protect the semiconductor component against damage when the parasitic thyristor is triggered.

16. A semiconductor component according to claim 1 , wherein the sensitivity of the parasitic thyristor to light attacks is a function of the resistance of the resistor.

17. A semiconductor component according to claim 1 , wherein the sensitivity of the parasitic thyristor to light attacks is a function of a layer construction of the semiconductor component.

Assignees

• Infineon Technologies Ag

Inventors

• Kuenemund Thomas
• Tischendorf Dennis
• Weder Uwe

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W42/40

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H03K19/17768 Primary

  for security · CPC title