Non-linearity cancellation in a dual-path ADC

Patent metadata

Field	Value
Publication number	US-9503112-B1
Application number	US-201615154769-A
Country	US
Kind code	B1
Filing date	May 13, 2016
Priority date	May 13, 2016
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancellation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a first analog to digital converter (ADC) configured to receive an input signal from an input terminal and generate a first digital signal;
a second ADC configured to receive the input signal from the input terminal and generate a second digital signal, wherein the second digital signal is more non-linear than the first digital signal; and
a digital signal processing block configured to:
receive the first digital signal and the second digital signal;
determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals; and
modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

2. The apparatus of claim 1 , wherein the digital signal processing block is configured to:
generate one or more non-linear components of the second digital signal based, at least in part, on the determined one or more non-linear coefficients; and
subtract the generated one or more non-linear components from the second digital signal.

3. The apparatus of claim 1 , wherein the first ADC comprises a closed-loop ADC.

4. The apparatus of claim 1 , wherein the second ADC comprises an open-loop voltage controlled oscillator-based (VCO-based) ADC.

5. The apparatus of claim 1 , wherein the second ADC is configured to amplify the received input signal.

6. The apparatus of claim 1 , wherein the digital signal processing block is further configured to:
filter the first and second digital signals; and
select one of the filtered first digital signal and the filtered second digital signal for further processing.

7. The apparatus of claim 6 , wherein the digital signal processing block being configured to:
select the filtered first digital signal when a signal strength associated with the input signal is equal to or exceeds a threshold signal strength; and
select the filtered second digital signal when the signal strength associated with input signal is less than the threshold signal strength.

8. The apparatus of claim 1 , wherein the first ADC is further configured to receive input signals having an amplitude higher than input signals for which the second ADC is configured to receive.

9. A method, comprising:
receiving a first digital signal from a first analog to digital converter (ADC);
receiving a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal;
determining one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals; and
modifying the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

10. The method of claim 9 , wherein the step of modifying comprises:
generating one or more non-linear components of the second digital signal based, at least in part, on the determined one or more non-linear coefficients; and
subtracting the generated one or more non-linear components from the second digital signal.

11. The method of claim 9 , further comprising:
filtering the first and second digital signals; and
selecting one of the filtered first digital signal and the filtered second digital signal for further processing.

12. The method of claim 11 , wherein the step of selecting comprises:
selecting the filtered first digital signal when a signal strength associated with an input signal used to generate the first digital signal is equal to or exceeds a threshold signal strength; and
selecting the filtered second digital signal when the signal strength associated with the input signal used to generate the second digital signal is less than the threshold signal strength.

13. An apparatus, comprising:
a controller configured to perform steps comprising:
receive a first digital signal from a first analog to digital converter (ADC);
receive a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal;
determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals; and
modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

14. The apparatus of claim 13 , wherein modifying, by the controller, comprises the controller being further configured to perform the steps comprising:
generating one or more non-linear components of the second digital signal based, at least in part, on the determined one or more non-linear coefficients; and
subtracting the generated one or more non-linear components from the second digital signal.

15. The apparatus of claim 13 , wherein the first ADC comprises a closed-loop ADC.

16. The apparatus of claim 13 , wherein the second ADC comprises an open-loop voltage controlled oscillator-based (VCO-based) ADC.

17. The apparatus of claim 13 , wherein the controller is further configured to perform steps comprising:
filtering the first and second digital signals; and
selecting one of the filtered first digital signal and the filtered second digital signal for further processing.

18. The apparatus of claim 17 , wherein selecting, by the controller, comprises the controller being further configured to perform steps comprising:
selecting the filtered first digital signal when a signal strength associated with an input signal used to generate the first digital signal is equal to or exceeds a threshold signal strength; and
selecting the filtered second digital signal when the signal strength associated with the input signal used to generate the second digital signal is less than the threshold signal strength.

19. The apparatus of claim 13 , wherein the controller comprises an audio coder/decoder (CODEC).

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Zanbaghi Ramin
• Mortazavi Yousof
• Brennan Aaron
• Melanson John L

Classifications

• H03M1/1004

  without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated (H03M1/1009, H03M1/1071 take precedence) · CPC title

• H03M1/0602 Primary

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title

• H03M1/1042

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title

• H03M1/1038 Primary

  by storing corrected or correction values in one or more digital look-up tables (H03M1/1057 takes precedence) · CPC title

• H03M1/1205

  Multiplexed conversion systems · CPC title