Self-tracking and self-ranging window analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10447288-B2
Application number	US-201816227073-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Dec 20, 2017
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

This disclosure relates to an analog-to-digital converter, ADC. The ADC comprises a first detection and second detection line, each including a plurality of serially arranged detection units, where the detection units of the first line are controlled in accordance with a first signal and the detection units of the second line are controlled in accordance with a second signal, and each line comprises a first group of serially arranged detection units and a second group of serially arranged detection units, a pulse generator for generating a periodic pulse signal that is fed to each of the lines, a sampling unit configured to read out values held by the detection units of the first group in one of the first and second lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second lines, and a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second lines in accordance with a read out of the detection units of the first group of detection units.

First claim

What is claimed is:

1. An analog-to-digital converter, ADC, comprising:
a first detection line and a second detection line, each including a plurality of serially arranged detection units, wherein the detection units of the first detection line are controlled in accordance with a first signal and the detection units of the second detection line are controlled in accordance with a second signal and wherein each detection line comprises a first group of serially arranged detection units and a second group of serially arranged detection units;
a pulse generator for generating a periodic pulse signal that is fed to each of the first and second detection lines;
a sampling unit configured to read out values held by the detection units of the first group of detection units in one of the first and second detection lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second detection lines; and
a detection line control unit configured to adjust a delay of the second group of detection units in the one of the first and second detection lines in accordance with a read out of the detection units of the first group of detection units in the one of the first and second detection lines, wherein the delay of the second group of detection units is adjusted by selectively bypassing detection units.

2. The ADC according to claim 1 , wherein a number of bypassed detection units in the second group of detection units of the one of the first and second detection lines depends on a number of detection units in the first group of detection units of the one of the first and second detection lines that hold values indicating absence of a pulse on occurrence of the pulse of the pulse signal reaching the predetermined detection unit of the other one of the first and second detection lines.

3. The ADC according to claim 1 , wherein the number of bypassed detection units is chosen so that run through times of the first and second detection lines are substantially aligned.

4. The ADC according to claim 1 , wherein detection cells are bypassed for at most one of the first and second detection lines at a time.

5. The ADC according to claim 1 , wherein an output of the ADC depends on a sum of a number of detection units that are currently bypassed on occurrence of the pulse of the pulse signal reaching the predetermined detection unit of the other one of the first and second detection lines and the number of detection units in the first group of detection units of the one of the first and second detection lines that hold values indicating absence of a pulse on occurrence of the pulse of the pulse signal reaching the predetermined detection unit of the other one of the first and second detection lines.

6. The ADC according to claim 1 , wherein the delay of the second group of detection units in the one of the first and second detection lines is adjusted for a next pulse of the pulse signal.

7. The ADC according to claim 1 , wherein the first signal and the second signal are indicative of an input analog signal differential and are offset from a common mode signal by opposite signs.

8. The ADC according to claim 1 , wherein the first signal is indicative of a fixed reference analog signal and the second signal is indicative of an input analog signal.

9. The ADC according to claim 8 , wherein the one of the first and second detection lines is the second detection line and the other one of the first and second detection lines is the first detection line.

10. The ADC according to claim 1 , wherein the detection line control unit is further configured to adjust a delay of the second group of detection units in the first detection line and a delay of the second group of detection units in the second detection line by the same amount, by selectively bypassing detection units.

11. The ADC according to claim 10 , wherein the delay of the second group of detection units in the first detection line and the delay of the second group of detection units in the second detection line are adjusted in accordance with a desired resolution of the ADC.

12. The ADC according to claim 1 , further comprising an input stage, the input stage including one or more operational amplifiers for generating the first and second signals from one or more input analog signals.

13. A delay line analog-to-digital converter, ADC, comprising:
a first detection line and a second detection line, each including a plurality of serially arranged detection units, wherein the detection units of the first detection line are controlled in accordance with a first signal and the detection units of the second detection line are controlled in accordance with a second signal and wherein each detection line comprises a first group of serially arranged detection units and a second group of serially arranged detection units;
a pulse generator for generating a periodic pulse signal that is fed to each of the first and second detection lines;
a sampling unit configured to read out values held by the detection units of the first group of detection units in one of the first and second detection lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second detection lines; and
a detection line control unit configured to adjust a delay of the second group of detection units in the first detection line and a delay of the second group of detection units in the second detection line by the same amount, by selectively bypassing detection units.

14. The ADC according to claim 13 , wherein the delay of the second group of detection units in the first detection line and the delay of the second group of detection units in the second detection line are adjusted in accordance with a desired resolution of the ADC.

15. A method of operating an analog-to-digital converter, ADC, the ADC comprising a first detection line and a second detection line, each including a plurality of serially arranged detection units, wherein the detection units of the first detection line are controlled in accordance with a first signal and the detection units of the second detection line are controlled in accordance with a second signal and wherein each detection line comprises a first group of serially arranged detection units and a second group of serially arranged detection units,
the method comprising:
generating a periodic pulse signal and feeding the periodic pulse signal to each of the first and second detection lines;
reading out values held by the detection units of the first group of detection units in one of the first and second detection lines on occurrence of a pulse of the pulse signal reaching a predetermined detection unit of the other one of the first and second detection lines; and
adjusting a delay of the second group of detection units in the one of the first and second detection lines in accordance with a read out of the detection units of the first group of detection units in the one of the first and second detection lines, wherein the delay of that second group of detection units is adjusted by selectively bypassing detection units.

16. The method according to claim 15 , wherein the number of bypassed detection units in the second group of detection units of the one of the first and second detection lines depends on the number of detection units in the first group of detection units of the one of the first and second detection lines that hold values indicating absence of a pulse on occurrence of the pulse of the pulse signal reaching the predetermined detection unit of

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Muhoberac Ivan

Classifications

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/502 Primary

  using tapped delay lines · CPC title

• H03M1/007 Primary

  among different resolutions · CPC title

• H03M1/0602

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title