Active switch having low leakage current

Patent metadata

Field	Value
Publication number	US-10033396-B1
Application number	US-201715469564-A
Country	US
Kind code	B1
Filing date	Mar 26, 2017
Priority date	Mar 26, 2017
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

In an analog-to-digital converter (ADC) having storage capacitors, active, top-plate, n-type, switch circuitry has an n-type transistor and gate-voltage control circuitry that generates the gate voltage to turn on and off the transistor. The control circuitry turns off the transistor by generating the gate voltage at a level that limits the gate-to-source voltage difference, thereby limiting GISL leakage current through the transistor that can otherwise jeopardize the accuracy of the ADC digital output value. In one implementation, when the transistor is to be off (for example, during the ADC conversion phase), the control circuitry generates the gate voltage to be at ground if the source voltage is below a reference voltage, and above ground if the source voltage is above the reference voltage. The switch circuitry can also be implemented using a p-type device or a transmission gate instead of the n-type device.

First claim

The invention claimed is:

1. An analog-to-digital converter (ADC), comprising switch circuitry connected between an ADC voltage reference and ADC storage capacitors, wherein the switch circuitry comprises:
a transistor device having a gate terminal connected to receive a gate voltage, a first channel terminal connected to a common-mode reference voltage, a second channel terminal connected to receive a second-channel-terminal voltage, and a body terminal connected to ground; and
gate-voltage control circuitry that generates the gate voltage to turn on and off the transistor device, wherein the gate-voltage control circuitry turns off the transistor device by generating the gate voltage at a level that limits voltage difference between the gate voltage and the second-channel-terminal voltage to control OFF-state leakage of the transistor device, thereby limiting leakage current through the transistor device, and
wherein the gate-voltage control circuitry comprises:
a sense circuit that compares the second-channel-terminal voltage to a reference voltage and generates a comparison signal indicating the comparison result;
digital control logic that generates a multi-bit control signal based on the comparison signal and a switch-enable control signal; and
a gate-voltage generator that generates the gate voltage based on the multi-bit control signal, and wherein the sense circuit comprises:
a comparator with hysteresis that receives the second-channel-terminal voltage and the reference voltage, and generates the comparison signal; and
a voltage divider comprising a plurality of resistors for generating the reference voltage,
wherein the hysteresis prevents the comparison signal from toggling when the second-channel-terminal voltage and the reference voltage are substantially equal.

2. The ADC of claim 1 , wherein:
the transistor device is an n-type device;
the first channel terminal is the drain terminal of the transistor device;
the second channel terminal is the source terminal of the transistor device; and
the gate-voltage control circuitry generates the gate voltage at a non-ground level when the source voltage of the transistor device is at or near a supply voltage for the switch circuitry.

3. The ADC of claim 2 , wherein the gate-voltage control circuitry generates the gate voltage at a ground level when the source voltage of the transistor device is not at or near the supply voltage.

4. The ADC of claim 3 , wherein:
the gate-voltage control circuitry compares the source voltage of the transistor device to a reference voltage;
the gate-voltage control circuitry generates the gate voltage at the ground level, if the gate-voltage control circuitry determines that the source voltage of the transistor device is below the reference voltage; and
the gate-voltage control circuitry generates the gate voltage at the non-ground level, if the gate-voltage control circuitry determines that the source voltage of the transistor device is above the reference voltage.

5. The ADC of claim 1 , wherein:
the transistor device is an n-type device;
the first channel terminal is the drain terminal of the transistor device;
the second channel terminal is the source terminal of the transistor device;
the sense circuit compares the source voltage of the transistor device to the reference voltage and generates the comparison signal indicating the comparison result;
the gate-voltage generator generates the gate voltage at a supply level for the switch circuitry if the digital control logic determines that the switch-enable control signal indicates that the transistor device is to be on;
the gate-voltage generator generates the gate voltage at a ground level for the switch circuitry if the digital control logic determines that the switch-enable control signal indicates that the transistor device is to be off and if the sense circuit determines that the source voltage of the transistor device is below the reference voltage; and
the gate-voltage generator generates the gate voltage at a non-ground level if the digital control logic determines that the switch-enable control signal indicates that the transistor device is to be off and if the sense circuit determines that the source voltage of the transistor device is above the reference voltage.

6. The ADC of claim 1 , wherein the ADC is a successive-approximation-register (SAR) ADC.

7. The ADC of claim 1 , wherein the comparator comprises a differential transistor pair with a current mirror as an active load.

8. The ADC of claim 1 , wherein the digital control logic comprises:
a first inverter that receives the switch-enable control signal and generates a first bit of the multi-bit control signal (ph 0 );
a NOR gate that receives the switch-enable control signal and the second-channel-terminal voltage, and generates a second bit of the multi-bit control signal (ph 1 );
a NAND gate that receives the first bit of the multi-bit control signal and the second-channel-terminal voltage, and generates a third bit of the multi-bit control signal (ph 2 ); and
a second inverter that receives the third bit of the multi-bit control signal and generates a fourth bit of the multi-bit control signal (ph 3 ).

9. The ADC of claim 8 , wherein the gate-voltage generator comprises:
a first p-type MOSFET transistor (M 14 ) having a gate that receives the first bit of the multi-bit control signal (ph 0 );
a first n-type MOSFET transistor (M 15 ) having a gate that receives the second bit of the multi-bit control signal (ph 1 ), a drain connected to a drain of the first p-type MOSFET transistor, a source connected to ground, and a body connected to ground;
a second p-type MOSFET transistor (M 16 ) having a gate that receives the third bit of the multi-bit control signal (ph 2 ), and a source connected to a source of the first p-type MOSFET transistor device (M 14 );
a second n-type MOSFET transistor (M 17 ) having a gate that receives the fourth bit of the multi-bit control signal (ph 3 ), a drain connected to a drain of the second p-type MOSFET transistor (M 16 ) by way of a pair of resistors (R 3 , R 4 ), a source connected to the source of the first n-type MOSFET transistor (M 15 ), and a body connected to ground,
wherein a node between the first p-type MOSFET transistor (M 14 ) and the first n-type MOSFET transistor (M 15 ) is connected to a node between the pair of resistors (R 3 , R 4 ), and the gate voltage is generated at said node.

Assignees

• Nxp Usa Inc

Inventors

• Pandey Luv
• Dey Sanjoy Kumar

Classifications

• H03K17/161 Primary

  in field-effect transistor switches · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title